Abstract: A power detector is described herein that detects a true power provided by power amplifier of an RF transmitter. The power detector may include a plurality of voltage detectors that determine one or more voltages of a power amplifier included in the RF transmitter and/or a transformer included in the RF transmitter. At least one of the voltage detectors may be coupled to a sense inductor that senses one or more magnetic fields emitted by the transformer. The at least one voltage detector coupled to the sense inductor determines the voltage induced across the sense inductor as a result of the sensed magnetic field(s). The determined voltage(s) may be used to determine the load impedance of an antenna of the RF transmitter that transmits the RF signals. The load impedance may be used to accurately measure the power regardless of any impedance mismatches between the power amplifier and the antenna.

Abstract: A power detector is described herein that detects a true power provided by power amplifier of an RF transmitter. The power detector may include a plurality of voltage detectors that determine one or more voltages of a power amplifier included in the RF transmitter and/or a transformer included in the RF transmitter. At least one of the voltage detectors may be coupled to a sense inductor that senses one or more magnetic fields emitted by the transformer. The at least one voltage detector coupled to the sense inductor determines the voltage induced across the sense inductor as a result of the sensed magnetic field(s). The determined voltage(s) may be used to determine the load impedance of an antenna of the RF transmitter that transmits the RF signals. The load impedance may be used to accurately measure the power regardless of any impedance mismatches between the power amplifier and the antenna.

Abstract: A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.

Abstract: A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.

Abstract: A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.

Abstract: A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.

Abstract: A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances.

Abstract: A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.

Abstract: Systems and methods are provided for reducing the peak to average ratio of signals, so that the signals can be amplified more efficiently. An error signal that corresponds to crests of the input signal is generated, and subtracted from the input signal. When a crest is so long that it corresponds to more than one sample, only the maximum sample contained in the crest is used to form the error signal. Optionally, multiple stages of decresting may be implemented sequentially.

Abstract: Second-order harmonic tuning of an active device, such as a transistor used in a radio frequency (RF) power amplifier circuit, is accomplished by positioning a quarter-wavelength stub along a transmission line coupled to an output of the device, such that the output is presented with a desired impedance for the second harmonic.

Abstract: Second-order harmonic tuning of an active device, such as a transistor used in a radio frequency (RF) power amplifier circuit, is accomplished by positioning a quarter-wavelength stub along a transmission line coupled to an output of the device, such that the output is presented with a desired impedance for the second harmonic.

Abstract: Systems and methods are provided for reducing the peak to average ratio of signals, so that the signals can be amplified more efficiently. An error signal that corresponds to crests of the input signal is generated, and subtracted from the input signal. When a crest is so long that it corresponds to more than one sample, only the maximum sample contained in the crest is used to form the error signal. Optionally, multiple stages of decresting may be implemented sequentially.