Patents by Inventor Heng Yu Kung

Heng Yu Kung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10605828
    Abstract: A device used for attaching a semiconductor device to a circuit board over a first temperature. The device includes a hook member that includes a first hook, a second hook, and a body between the first hook and the second hook. The body has a first surface, a second surface opposite the first surface, and a first hole extended from the first surface to the second surface. The device further includes a fixing member and a holder. The fixing member has a second hole, and the holder passes through the first hole and the second hole, and is engaged with the fixing member.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 31, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Heng Yu Kung, Shu-Hsien Lee
  • Publication number: 20180284152
    Abstract: A device used for attaching a semiconductor device to a circuit board over a first temperature. The device includes a hook member that includes a first hook, a second hook, and a body between the first hook and the second hook. The body has a first surface, a second surface opposite the first surface, and a first hole extended from the first surface to the second surface. The device further includes a fixing member and a holder. The fixing member has a second hole, and the holder passes through the first hole and the second hole, and is engaged with the fixing member.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Heng Yu KUNG, Shu-Hsien LEE
  • Patent number: 6788092
    Abstract: A test assembly for an integrated circuit package includes a package substrate and a test board. The package substrate is provided with a plurality of first contact pads linked in a first daisy chain pattern. The test board has a plurality of second contact pads linked in a second daisy chain pattern and a plurality of test pads. All of the second contact pads are divided into a plurality of groups each connected to one pair of test pads. All of the second contact pads in any group are arranged in a line. The present invention further provides a method of testing an integrated circuit package utilizing the aforementioned package substrate and test board.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: September 7, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Po Jen Cheng, Chiu Wen Lee, Jin Zhu Lee, Heng Yu Kung
  • Publication number: 20040155241
    Abstract: A test assembly for an integrated circuit package includes a package substrate and a test board. The package substrate is provided with a plurality of first contact pads linked in a first daisy chain pattern. The test board has a plurality of second contact pads linked in a second daisy chain pattern and a plurality of test pads. All of the second contact pads are divided into a plurality of groups each connected to one pair of test pads. All of the second contact pads in any group are arranged in a line. The present invention further provides a method of testing an integrated circuit package utilizing the aforementioned package substrate and test board.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 12, 2004
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po Jen Cheng, Chiu Wen Lee, Jin Zhu Lee, Heng Yu Kung
  • Publication number: 20030193344
    Abstract: A test assembly for an integrated circuit package includes a package substrate and a test board. The package substrate is provided with a plurality of first contact pads linked in a first daisy chain pattern. The test board has a plurality of second contact pads linked in a second daisy chain pattern and a plurality of test pads. All of the second contact pads are divided into a plurality of groups each connected to one pair of test pads. All of the second contact pads in any group are arranged in a line. The present invention further provides a method of testing an integrated circuit package utilizing the aforementioned package substrate and test board.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 16, 2003
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po Jen Cheng, Chiu Wen Lee, Jin Zhu Lee, Heng Yu Kung