Abstract: A static RAM bit cell and a system and method for operating an array of such static RAM bit cells. The static RAM bit cell herein includes a cell of four transistors configured to store data. It also includes a pair of word line pass transistors and a pair of column pass transistors coupled to the cell of four transistors. The word line pass transistors are coupled to a word line such that they can be opened in closed in response to a signal on the word line. The column pass transistors are coupled to a column select transistor such that they can be opened and closed in response to a signal on the column select line. Using this configuration signals can be generated on the word line and the column select line so that only a small fraction of the total number of static RAM bit cells in an array need to be charged and discharged in connection with performing read and write operations to a specific static RAM bit cell.

Abstract: The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.

Abstract: An ESD protection device for use with an integrated circuit that provides a low impedance resistive path between IC pads (including Vdd and Vss pads) when power to the IC is off, while assuring adequate isolation between the IC pads when the power is on. The device includes a semiconductor substrate (typically a p-type Si substrate) and at least two vertically integrated pinch resistors formed in the semiconductor substrate. Each of the vertically integrated pinch resistors is connected to a common electrical discharge line and to a pad. Each of the vertically integrated pinch resistors includes a deep well region and a first surface well region, both of the second conductivity type (typically n-type). The first surface well region circumscribes the deep well region, thereby forming a narrow channel region of the first conductivity type (e.g. p-type) therebetween. When no potential is applied to the first surface well regions (i.e.

Abstract: A low capacitance multilevel metal interconnect structure for use in integrated circuits that provides for increased IC device speed and that includes a plurality of patterned metal layers separated and supported by an interconnect dielectric material. The low capacitance multilevel metal interconnect structure has interconnect structure related capacitance lowering gaps in the interconnect dielectric material with the gaps, adjoining at least one of the patterned metal layers. While the gaps adjoin at least the uppermost patterned metal layer, they can also extend downward through the interconnect dielectric material such that they also adjoin one or more patterned metal layers that underlie the uppermost patterned metal layer. A process for the manufacture of the low capacitance multilevel metal interconnect structure includes a step of removing interconnect dielectric material from a conventional multilevel metal interconnect structure to form gaps adjoining at least one of the patterned metal layers.