Abstract: The invention relates to a housing for a semiconductor device and a novel semiconductor device testing system, in particular for testing the contacting of semiconductor devices positioned one above the other, which increases the parallelism during testing, is solved by the present invention in that recesses or notches, respectively, are provided in the housing for a semiconductor device, via which at least one internal contact line (bond wire) that connects an integrated circuit with external contacts (pins) can be contacted from outside, in particular for performing semiconductor device tests. The resulting advantage is that, for testing the semiconductor device or semiconductor module, respectively, not only the external contacts (pins), but also the recesses or notches, respectively, in the housing of the semiconductor device or semiconductor module, respectively, can be used for contacting.

Abstract: The invention relates to a memory component (11), with numerous contact connections (12a, 12b, 12c), and with at least two memory cell arrays (13a, 13b), each containing numerous memory cells, whereby the contact connections (12a, 12b, 12c) are arranged to lie in an area (17) between a central axis (a)—running between the arrays (13a, 13b)—, in particular the spine of the memory component (11), and one of the arrays (13a).

Abstract: A test configuration that includes a device and a method for testing the device in which test results determined during the testing of the device are stored in a memory in the device. In this way, the test results are connected with the device and available at any time for later evaluations.

Abstract: A test configuration that includes a device and a method for testing the device in which test results determined during the testing of the device are stored in a memory in the device. In this way, the test results are connected with the device and available at any time for later evaluations.

Abstract: A data driver is activated in dependence of a provided bit sequence in order to produce, at the data output of the driver, a data signal which, in the times between periodic reference clock pulse edges, is in each case driven to a high or low validity level in accordance with the binary value of the bits of the provided bit sequence. Directly before selected reference clock pulse edges, a preparation interval of a fixed length is provided, during which the driver is prompted to drive its data output to a medium level between the high validity level and the low validity level. The length of the preparation interval is at least equal to the response time necessary to drive the data output over the level difference between one of the validity levels and the medium level, but is shorter than twice this response time.

Abstract: A data driver is activated in dependence of a provided bit sequence in order to produce, at the data output of the driver, a data signal which, in the times between periodic reference clock pulse edges, is in each case driven to a high or low validity level in accordance with the binary value of the bits of the provided bit sequence. Directly before selected reference clock pulse edges, a preparation interval of a fixed length is provided, during which the driver is prompted to drive its data output to a medium level between the high validity level and the low validity level. The length of the preparation interval is at least equal to the response time necessary to drive the data output over the level difference between one of the validity levels and the medium level, but is shorter than twice this response time.