Abstract: A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory.

Abstract: A temperature estimation circuit for estimating a temperature of an integrated circuit die comprises a temperature increase estimation circuit, having inputs operable to receive notification signals, each corresponding to a command signal passed to an integrated circuit, and an output providing a sum of temperature increase values, each corresponding to a temperature increase of the integrated circuit due to one of the command signals. The circuit further comprises a temperature decrease estimation circuit, having an input operable to receive a calculated die temperature value, and an output providing a temperature decrease value depending on a mathematical model of temperature decrease when no command signal is applied.

Abstract: A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory.

Abstract: A temperature estimation circuit for estimating a temperature of an integrated circuit die comprises a temperature increase estimation circuit, the circuit has one or more inputs operable to receive one or more notification signals corresponding to command signals passed to the integrated circuit, and an output providing a sum of one or more temperature increase values, corresponding to temperature increase of the integrated circuit due to one of the command signals. The circuit may further have a temperature decrease estimation circuit, comprising an input operable to receive a calculated die temperature value, and an output providing a temperature decrease value depending on a mathematical model of temperature decrease when no command signal is applied.

Abstract: A system (10) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user programmed address permutation control registers (70-72) is used to determine what bit values are used to replace predetermined bits of the input address to selectively create a corresponding permutated address. Since no modification to a processor's pipeline is required, various permutation addressing modes may be user-defined and implemented using either a general-purpose processor or a specialized processor.

Abstract: A system (10) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user programmed address permutation control registers (70-72) is used to determine what bit values are used to replace predetermined bits of the input address to selectively create a corresponding permutated address. Since no modification to a processor's pipeline is required, various permutation addressing modes may be user-defined and implemented using either a general-purpose processor or a specialized processor.

Abstract: A decoding device and method for a data stream that represents a user signal and makes up multi-symbol words that are protected against burst errors. In case of a discontinuity, a FIFO jump may occur in the decoding device. Subsequently, de-interleaving may occur, and this will cause the multi-symbol words to be made up from symbols which occur before and after the discontinuity. If this is the case, within such words, the minority symbols are flagged. If too many words have an excessive number of flags, error correction will fail. If so, an error concealment operation occurs, but the number of such concealments is kept minimum. This will decrease the subjective quality of the user signal by only a minimum amount.

Abstract: A phase locked loop includes a capture aid circuit to pull the frequency of the oscillator towards the bit frequency of a data signal HF.sub.in consisting of pulses of variable lengths, each length being an integral multiple of a single bit basic length unit. The capture aid circuit includes a pulse length detector for measuring and rounding pulse length to the nearest integral number of basic length units, and determining the difference (.DELTA.RL) between the measured and rounded length value (RL). For small frequency deviations the rounding error (.DELTA.RL) signal is used as a frequency deviation control signal for increasing or decreasing the oscillator frequency. For larger frequency deviations the minimum pulse length will be either more or less than a predetermined number of length units.

Abstract: A digital control system includes an actuator (2) for controlling a state variable of a process, a sensor (3) for detecting the state variable, and an A/D converter (4) for converting the measured state variable into a series of m-bit digital signal words I(k). These are processed by a digital processor (5) which includes a digital subcircuit (6) for normalizing the signal words I(k) and/or stablizing the gain of the control system. The subcircuit (6) includes a comparator circuit (21) which receives at an input thereof a series of m-bit signal words a(k) related to the series of measured signal words I(k), the converter being in series with an integrating filter (24) and a quantizing circuit (25). A multiplier (20) is connected in a negative feedback path from the output of the subcircuit to another input of the comparator (21).

Abstract: A read and/or write device for a record carrier having tracks which extend substantially parallel to each other. A read and/or write head for scanning the tracks is moved by a positioning system in a direction transverse to the tracks. During such movement a counter derives the number of tracks traversed per unit time from the number of reference level crossings of a periodic signal V.sub.sp having a frequency corresponding to the track crossing frequency. Counting of spurious level crossings is inhibited by blocking the counter during a blocking interval (tbl) following each level crossing which is counted. The speed of the read and/or write head is controlled on the basis of the counted level crossings.