Abstract: A micro electro-mechanical system (MEMS) variable capacitor is described, wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate and are independently actuated. The electrodes are formed in an interdigitated fashion to maximize capacitance. The MEMS variable capacitor includes CMOS manufacturing steps in combination with elastomeric material selectively used in areas under greatest stress to ensure that the varactor will not fail as a result of stresses that may result in the separation of dielectric material from the conductive elements. The combination of a CMOS process with the conducting elastomeric material between vias increases the overall sidewall area, which provides increased capacitance density.

Abstract: A method and circuitry for testing in situ the components mounted on a circuit board. First, a component is removed from the board. A testing circuit is then installed in place of the removed component. The testing circuit allows test patterns to be applied to a selected component on the board from the board I/O pins. The selected component responses are collected by the testing circuit and applied to the board output pins. In this manner, individual components on the board can be tested in situ from pins on the board.

Abstract: An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connected the packaging structure to the next level of packaging (i.e., board or card).The thin film wiring layers typically each having coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes.

Abstract: A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site.

Abstract: A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes.

Abstract: A system for automatically testing a plurality of memory arrays on selected memory array testers includes an interactive data entry device for entering array test specifications including characterizing information, DC testing parameters, AC testing parameters and AC test pattern choices for the array. The test specifications are entered in a format which is independent of a particular tester's characteristics. A universal language generator generates a tester independent universal language instruction sequence for carrying out the prescribed tests based upon the entered test specifications. Associated with each tester is a universal language translator which translates the tester independent universal language instruction sequence into an instruction sequence which is particular to the associated tester. The tester dependent instruction sequence may be loaded into the associated tester to produce the test signals for testing the memory array.

Abstract: A method and apparatus for testing large or very large scale integrated circuit packages is described. The testing equipment required for testing such packages is assumed to lack the number of channels necessary to connect one channel to each input/output of the unit under test. A computer program classifies all input terminals in a plurality of categories, each of which corresponds to particular circuit type and electric network configuration connected to that pin. A unique set of DC levels is defined prior to testing for each class of inputs. These levels are supplied by the tester channels, each of which drives a multitude of input pins that belong to the same category. The assignment of tester channels in the aforementioned arrangement is implemented by means of multiplexers that select for each pin the appropriate set of DC levels, and a memory buffer contained in the tester, with the DC test patterns stored wherein.