Abstract: A low-rate encoding/digital speech interpolation (LRE/DSI) system architecture is organized to eliminate the LRE mistracking problem normally associated with DSI-induced speech clipping, to reduce the number of LRE codes required and to provide a mechanism for gradually introducing overload.

Abstract: An adaptive gain control is provided at the input of a Variable Rate Nearly Instantaneous Companding (VRNIC) processor to adjust the gain of low level speech signals so that the transmission bit rate and SNR will remain substantially the same for low signal levels as for high signal levels.

Abstract: A robust ADPCM encoder with a modified leaky quantizer and a pair of parallel predictors is provided. A large leakage is initially inserted into the quantization scale adaptation by utilizing a number of most recent multipliers in a modified leaky Jayant quantizer. Using a dual predictor feedback loop, inside predictor coefficients are updated by the step size having unit variance instead of by the quantized prediction error.

Abstract: A nearly instantaneous companding processor uses variable precision block quantization for reducing the digital transmission rate of speech signals while at the same time maintaining a high quality signal in a digital communication system. The variable number of bits which are used to encode each sample is controlled as a function of the maximum sample magnitude in a block of N samples. This technique takes advantage of the amplitude probability density function of a speech signal to thereby reduce the quantizing noise without increasing the transmission rate.

Abstract: An automatic H-register clear system for the prevention of erroneous convolution in adaptive digital echo cancellers is disclosed. Incoming signals from the H-register are accumulated and compared to a predetermined threshold value and when the value is exceeded, the H-register is cleared with the occurrence of the internal housekeeping cycle of the echo canceller. The clearing of the H-register allows a new impulse response model to be generated from new sampled data. In one embodiment using analog implementation, the accumulation takes place using a sequence of signal processing of digital-to-analog conversion, full wave rectification followed by integration of the signal. In another preferred embodiment using a counter detection system, each word is compared to a threshold and if this value is exceeded, a counter is indexed. If the value of the count in the counter exceeds a predetermined number during the sampling interval, the H-register is cleared.