Abstract: The invention provides an impedance adapter that automaticaly switches to impedances that match network transmit/receive lines impedances (105,106) by a controlled switching of various impedances mounted serially/parallely with connected transmitter/receiver (100,101). For a high speed adapter, a balanced transmitter/receiver is required for limiting crosstalk effect due to the high transmission rate. Transmit/Receive impedance adaptation networks (102-103) are composed of serial/parallel networks of resistors and relay contacts that are switched independently by magnetic coils of an impedance switching circuit (110) and having values conformable to the various network impedances imposed by different national regulations. By using the principle of double deviation voltage technique, a measuring circuit (108) detects upward and downward voltages (VA,VB), VB amplified by 2 to generate an analog signal VS (VS=VA-2VB) to a control logic circuit (109).

Abstract: An adapter having a line interface circuit for providing an analog attachment to a network (100). The line interface circuit is provided with a reset input for beginning a resynchronization of the timing of the adapter. The adapter further includes a Digital Phase-locked Loop device DPLL (203) driven by a master clock (306) which provides the timing and synchronization signals to the line interface circuits (201). The DPLL (203) divides a master clock down to an internal INT clock (309), a phase comparator (303) compares the INT clock with a reference signal (302) which is synchronized with the receive clock (202) extracted from the line by line interface (201). The phase comparison process operates with a Correction Signal (CS) which has a window centered around the falling edge of the INT clock. A frequency correction is initiated when the reference clock falls outside of the correction window and is achieved by inserting or suppressing a master clock pulse at this time.