Abstract: An instruction processing circuit comprises an instruction decoder (120, 121, 122), with an instruction input coupled to an instruction source (10) and a control output coupled to the control input of an execution circuit (124). The instruction decoder (120, 121, 122) comprises a plurality a predecoding circuit (120) with an input coupled to the instruction input and outputs coupled to control inputs of freezing circuits (121), which feed respective parallel sub-decoders 122. The predecoding circuit (120) detects to which type of instruction a supplied instruction belongs, and controls, dependent on the detected type, to which of the sub-decoding circuits (122) instruction information derived from the supplied instruction will be passed and to which of the sub-decoding circuits (122) supply of instruction information derived from a previously supplied instruction will be frozen.

Abstract: A digital signal processing integrated circuit contains an array of interconnected and programmed or programmable digital signal processors (10). Configurable multiplexing circuits (12), are placed between IO connections (11a,b) and the IO ports of at least a plurality of the digital signal processors (10). The multiplexing circuits (12) are configured under control of configuration data, so that the multiplexing circuit (12) give the effect of accessing the IO connection only to IO signals from the IO port or ports of one or ones of the respective plurality of digital signal processors (10) that are selected by the configuration data. Preferably, each digital signal processor (10) has its IO part coupled in common to a plurality of the multiplexing circuits (12) separately from the other digital signal processing circuits.

Abstract: A plurality of digital signal processors (10), each contains a signal processing core (22), a memory (20) coupled to the processing core (22) and a multiplexed data input (16) coupled to the memory (20). Each digital signal processor has a plurality of outputs for outputting data from the signal processing core (22). A remote write only structure (14a-d) couples outputs of respective groups of the digital signal processors (10) each to the multiplexed data input (16) of respective particular digital signal processor (10), the respective group for the particular digital signal processor (10) not including the particular digital signal processor (10). Thus, each processor (10) writes data for other processors directly from the processor, without storing the data in memory first for handling by an I/O processor, and reads data from other processors (10) via memory, where it is received via an input that does not share resources with the output of the processor (10).