Patents by Inventor Henrik Fredriksson
Henrik Fredriksson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979166Abstract: A method of weight calibration in a DAC (25) is disclosed. The DAC (25) comprises an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample, and a digital control circuit (110) configured to encode each digital input word (x[n]) into a control word (z[n]) representing the same digital input sample. Each bit (Zi) in the control word (z[n]) has a corresponding bit weight (wi) and is in the following considered to adopt values in {?1, 1}. Furthermore, the DAC (25) comprises a set (120) of analog weights, each associated with a unique one of the bits (Zi) in the control word (z[n]), and summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word (Zi) weighted by the respective associated analog weights. The DAC (25) also has an output (140) for outputting the analog sample.Type: GrantFiled: December 5, 2019Date of Patent: May 7, 2024Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)Inventor: Henrik Fredriksson
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Patent number: 11581895Abstract: An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (1051-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70j).Type: GrantFiled: February 27, 2019Date of Patent: February 14, 2023Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)Inventors: Henrik Fredriksson, Henrik Sjöland
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Publication number: 20230030923Abstract: A method of weight calibration in a DAC (25) is disclosed. The DAC (25) comprises an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample, and a digital control circuit (110) configured to encode each digital input word (x[n]) into a control word (z[n]) representing the same digital input sample. Each bit (Zi) in the control word (z[n]) has a corresponding bit weight (wi) and is in the following considered to adopt values in {?1, 1}. Furthermore, the DAC (25) comprises a set (120) of analog weights, each associated with a unique one of the bits (Zi) in the control word (z[n]), and summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word (Zi) weighted by the respective associated analog weights. The DAC (25) also has an output (140) for outputting the analog sample.Type: ApplicationFiled: December 5, 2019Publication date: February 2, 2023Inventor: Henrik Fredriksson
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Patent number: 11563426Abstract: A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.Type: GrantFiled: November 8, 2018Date of Patent: January 24, 2023Assignee: Telefonaktiebolaget LM Ericsson (Publ)Inventors: Henrik Sjöland, Henrik Fredriksson
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Patent number: 11349493Abstract: A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.Type: GrantFiled: April 13, 2021Date of Patent: May 31, 2022Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Henrik Fredriksson, Martin Anderson, Henrik Sjöland
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Publication number: 20220140835Abstract: An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (1051-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected.Type: ApplicationFiled: February 27, 2019Publication date: May 5, 2022Inventors: Henrik Fredriksson, Henrik Sjöland
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Patent number: 11265003Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.Type: GrantFiled: August 31, 2018Date of Patent: March 1, 2022Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)Inventors: Henrik Sjöland, Fredrik Tillman, Henrik Fredriksson, Lars Sundström
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Publication number: 20220006449Abstract: A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.Type: ApplicationFiled: November 8, 2018Publication date: January 6, 2022Inventors: Henrik SJÖLAND, Henrik FREDRIKSSON
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Publication number: 20210273645Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.Type: ApplicationFiled: August 31, 2018Publication date: September 2, 2021Inventors: Henrik Sjöland, Fredrik Tillman, Henrik Fredriksson, Lars Sundström
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Publication number: 20210234550Abstract: A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Inventors: Henrik Fredriksson, Martin Anderson, Henrik Sjöland
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Patent number: 11005493Abstract: A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.Type: GrantFiled: April 25, 2017Date of Patent: May 11, 2021Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Henrik Fredriksson, Martin Anderson, Henrik Sjöland
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Publication number: 20210050862Abstract: A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.Type: ApplicationFiled: April 25, 2017Publication date: February 18, 2021Inventors: Henrik Fredriksson, Martin Anderson, Henrik Sjöland
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Patent number: 10812100Abstract: A DAC (60) is disclosed. It comprises an input port comprising N input terminals p1, p2, . . . , pN configured to receive voltages representing N input bits b1, b2, . . . , bN, respectively, wherein the significance of bj is higher than for bj?1 for j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit (100) comprising N capacitors C1, C2, . . . , CN with capacitance C, each having a first terminal and a second terminal. Capacitor Cj is connected with its first terminal to the terminal pj of the input port. For each j=1, 2, . . . , N?1, the capacitor ladder circuit (100) comprises a capacitor (150j) with capacitance xC connected between the second terminal of capacitor Cj and the second terminal of capacitor Cj+1. The DAC (60) also comprises an input circuit (140) connected to the input port comprising at least one capacitor (1601-160N), each connected between a unique one of the input terminals p1, p2, . . . , pN of the input port and signal ground.Type: GrantFiled: June 16, 2017Date of Patent: October 20, 2020Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Martin Anderson, Henrik Fredriksson
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Publication number: 20200099390Abstract: A DAC (60) is disclosed. It comprises an input port comprising N input terminals p1, p2, . . . , pN configured to receive voltages representing N input bits b1, b2, . . . , bN, respectively, wherein the significance of bj is higher than for bj?1 for j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit (100) comprising N capacitors C1, C2, . . . , CN with capacitance C, each having a first terminal and a second terminal. Capacitor Cj is connected with its first terminal to the terminal pj of the input port. For each j=1, 2, . . . N?1, the capacitor ladder circuit (100) comprises a capacitor (150j) with capacitance xC connected between the second terminal of capacitor Cj and the second terminal of capacitor Cj+1. The DAC (60) also comprises an input circuit (140) connected to the input port comprising at least one capacitor (1601-160N), each connected between a unique one of the input terminals p1, p2, . . . , pN of the input port and signal ground.Type: ApplicationFiled: June 16, 2017Publication date: March 26, 2020Inventors: Martin Anderson, Henrik Fredriksson