Abstract: A radio receiver includes a low noise amplifier, a down conversion module, an analog to digital converter, and a digital demodulator. The low noise amplifier is operably coupled to amplify inbound radio frequency (RF) signals to produce amplified inbound RF signals. The down conversion module is operably coupled to convert the amplified inbound RF signals into low intermediate frequency (IF) signals. The analog to digital converter is operably coupled to convert the low IF signals into digital low IF signals. The digital demodulator is operably coupled to convert the digital low IF signals into inbound digital symbols and includes a baseband conversion module, a filtering module, a programmable equalizer, a CORDIC module, and a demodulation module. The baseband conversion module is operably coupled to convert the digital low IF signals into digital baseband signals. The filtering module is operably coupled to filter the digital baseband signals to produce filtered digital baseband signals.

Abstract: A digital delta sigma modulator includes an input integration stage, a resonating stage, a quantizer, and a plurality of feedback paths operably coupled to the quantizer, the input integration stage, and the resonating stage. The input integration stage is operably coupled to integrate a digital input signal to produce an integrated digital signal, wherein the input integration stage has a pole at substantially zero Hertz. The resonating stage is operably coupled to resonate the integrated digital signal to produce a resonating digital signal, wherein the resonating stage has poles at a frequency above zero Hertz. The quantizer stage is operably coupled to produce a quantized signal from the resonating digital signal.

Abstract: A method for designing an interpolation filter begins by partitioning interpolation filtering into a plurality of interpolation filtering stages that are cascaded together. Each of the plurality of interpolation filtering stages includes an up sampling stage and a filtering stage. The method continues by manipulating a first one of the interpolation filtering stages based on a first digital signal processing identity to produce a first equivalent interpolation filtering stage. The method continues by manipulating a second one of the interpolation filtering stages based on the first digital signal processing identity to produce a second equivalent interpolation filtering stage. The method continues by simplifying the first and second equivalent interpolation filtering stages to produce at least a simplified portion of the interpolation filter.

Abstract: An FSK modulator and applications thereof are disclosed. The FSK modulator comprises a phase-locked loop, a frequency divider module, an image rejection mixer and a summing module. The phase-locked loop is operably coupled to generate a first oscillation from a reference oscillation. The frequency divider module is operably coupled to divide the first oscillation to produce a second oscillation. The image-rejection mixer is operably coupled to mix the second oscillation with a low intermediate oscillation to produce a mixed data signal, and the summing module is operably coupled to sum the mixed data signal with the first oscillation to produce an FSK modulated signal.

Abstract: Radio transceiver circuitry includes I/Q imbalance compensation logic within at least one of a digital modulator or a digital demodulator, depending upon whether the I/Q imbalance compensation block is compensating for I/Q imbalance in a transmit path or in a receive path. For a transmitter, a digital processor includes a baseband processor that produces transmit data (digital data) for transmission to a digital modulator that includes an I/Q imbalance compensation logic. The digital modulator, which may modulate in any known modulation scheme, produces in-phase and quadrature phase components that have been pre-compensated for I/Q imbalance that is introduced by downstream analog circuitry in the transmit path. In at least one embodiment of the invention, a “steepest descent” algorithm for finding optimal values of I/Q imbalance compensation parameters based upon a small number of image rejection measurements are used.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: A digital modulator in a radio transmitter includes circuitry for switching between Gaussian Minimum Shift Keying (GMSK) and Phase-Shift Keying (PSK) while maintaining spectral mask requirements. The digital modulator of the present invention includes both GMSK and PSK symbol mappers that produce PSK in-phase and quadrature symbols and GMSK symbols, respectively, to a pulse shaping block. Based on opposite phases of a modulation control signal, the symbol mappers produce either modulated data or a steam of logic zeros to the pulse shaping block. The pulse shaping block filters the received data and multiplexes the data so that each modulated data stream receives non-zero data during a guard time to avoid abrupt changes in the modulated signal that would violate the spectral mask requirements.

Abstract: The present invention provides a radio transmitter having a digital modulator that further includes logic for continuous amplitude and continuous phase modulation switching in an RF transmitter intended to support both frequency shift keying (FSK) and phase shift keying (PSK) modulation techniques in a smooth and continuous manner that does not violate spectral mask requirements. The invention supports continuous modulation switching both ways, i.e., from FSK to PSK and from PSK to FSK. In operation, the radio transmitter initially operates in a first communication mode, transmitting communication signals to a remote agent according to a first modulation technique at a first data rate and then transitions to the second modulation type at a second data rate without spectral mask violation.

Abstract: A digital demodulator includes a mixing section, 1st and 2nd digital comb filters, phase locked loop module, and a data recovery module. The mixing section is operably coupled to produce a digital I signal and a digital Q signal from a digital intermediate frequency signal. The 1st comb filter filters the digital I signal while the 2nd comb filter filters the digital Q signal. The phase locked loop module produces a digital signal from the filtered I and filtered Q signals. The data recovery module interprets the digital signal to recapture a data stream.

Abstract: In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.

Abstract: In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by utilizing the Forward Error Correction (FEC) repetition rate in a header of a Bluetooth packet. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.

Abstract: A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the envelope of the translational loop at the translational loop output. The RF transmitter includes an Intermediate Frequency (IF) modulator, a translational loop, an envelope time delay adjust block, an envelope adjust block, and a time delay calibration block. The IF modulator receives a modulated baseband signal and produces a modulated IF signal having a non-constant envelope. The translational loop receives the modulated IF signal and produces a modulated RF signal having a constant envelope. The envelope time delay adjust block receives an envelope signal corresponding to the original modulated signal and produces a time delayed envelope signal based upon a time delay control signal. The envelope adjust block adjusts the modulated RF signal based upon the time delayed envelope signal to produce an envelope adjusted modulated RF signal.

Abstract: The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CTA??ADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CTA??ADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CTA??ADC loop. In one embodiment of the invention, random noise is added to the quantizer input.

Abstract: A digital demodulator that may be utilized in integrated radio receivers and/or integrated radios includes a mixing section, 1st and 2nd digital comb filters, phase locked loop module, and a data recovery module. The mixing section is operably coupled to produce a digital I signal and a digital Q signal from a digital intermediate frequency signal. The 1st comb filter filters the digital I signal while the 2nd comb filter filters the digital Q signal. The phase locked loop module produces a digital signal from the filtered I and filtered Q signals. The data recovery module interprets the digital signal to recapture a data stream.

Abstract: A digital filter with equalizers and a corresponding method for optimizing a linear equalizer of an RF transceiver determining filter characteristics of the specified analog filter, determining total signal filtering of the RF transceiver based upon a discrete time model of the specified analog filter and upon characteristics of the digital filter, determining an inverse of the determined total signal filtering; multiplying the inverse of the determined total signal filtering with the determined total signal filtering and optimally matching the desired equalizer filtering characteristic with an IIR magnitude equalizer to determine an optimal approximation of a magnitude response of the discrete time model of the specified analog filter. Thereafter, the method includes adding an inverse of the optimal approximation of the magnitude response and optimally matching the pre-distorting group delay response of the filter to obtain an optimal approximation to the pre-distorting group delay response of the filter.

Abstract: The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CT??ADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CT??ADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CT??ADC loop. In one embodiment of the invention, random noise is added to the quantizer input.

Abstract: A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop.

Abstract: Digital signal processing generates IF modulated digital data which is then converted to analog using a high sample rate digital-to-analog converter (DAC) without first producing a baseband signal that is to be upconverted to IF. The digital data has a high sample rate that is a whole multiple of a specified IF signal. A DAC converts the digital data into a continuous waveform IF signal that is produced to a feed-forward filter that eliminates spectral copies of the signal. The sample rate is selected so that harmonic signals do not appear in specified signal bands. Various embodiments include sample rates of 104 and 338 MHz (GSM application). The 26 MHz IF filtered signal produced by the feed-forward filter is then produced to a translational loop that produces a corresponding output oscillation (RF transmit signal).

Abstract: A method for calibrating a radio frequency (RF) transmitter begins by mixing a modulated RF signal with an in-phase (I) component of a local oscillation or a quadrature (Q) component of the local oscillation to produce a baseband representation of the modulated RF signal. The method continues by converting the baseband representation of the modulated RF signal into a digital baseband signal. The method continues by filtering the digital baseband signal to produce at least one frequency spectrum component. The method continues by interpreting the at least one frequency spectrum component to produce a calibration signal. The method continues by calibrating at least one of DC offset and gain offset of digital transmitter processing module based on the calibration signal.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.