Abstract: The present disclosure describes various chassis based antennas for a communication device. These various chassis based antennas can be integrated within a mechanical chassis of the communication device. The mechanical chassis is at least partially constructed of one or more conductive materials, such as copper or aluminum to provide some examples, or combinations of conductive materials, to provide one or more conductive paths for the communication device. The communication device can use these one or more conductive paths as one or more chassis based antennas for communication.

Abstract: The present disclosure describes various chassis based antennas for a communication device. These various chassis based antennas can be integrated within a mechanical chassis of the communication device. The mechanical chassis is at least partially constructed of one or more conductive materials, such as copper or aluminum to provide some examples, or combinations of conductive materials, to provide one or more conductive paths for the communication device. The communication device can use these one or more conductive paths as one or more chassis based antennas for communication.

Abstract: A digital delta sigma modulator includes an input integration stage, a resonating stage, a quantizer, and a plurality of feedback paths operably coupled to the quantizer, the input integration stage, and the resonating stage. The input integration stage is operably coupled to integrate a digital input signal to produce an integrated digital signal, wherein the input integration stage has a pole at substantially zero Hertz. The resonating stage is operably coupled to resonate the integrated digital signal to produce a resonating digital signal, wherein the resonating stage has poles at a frequency above zero Hertz. The quantizer stage is operably coupled to produce a quantized signal from the resonating digital signal.

Abstract: A digital delta sigma modulator includes an input integration stage, a resonating stage, a quantizer, and a plurality of feedback paths operably coupled to the quantizer, the input integration stage, and the resonating stage. The input integration stage is operably coupled to integrate a digital input signal to produce an integrated digital signal, wherein the input integration stage has a pole at substantially zero Hertz. The resonating stage is operably coupled to resonate the integrated digital signal to produce a resonating digital signal, wherein the resonating stage has poles at a frequency above zero Hertz. The quantizer stage is operably coupled to produce a quantized signal from the resonating digital signal.

Abstract: A method for processing a plurality of signals may include amplifying an input signal and generating a wideband signal from the amplified input signal. The method may further include bandpass filtering the generated wideband signal to generate a narrowband signal, and adjusting amplification of the input signal based on a narrowband received signal strength indication of the generated narrowband signal, and/or a wideband received signal strength indication of the generated wideband signal. The amplified input signal may be downconverted to generate the wideband signal. The amplified input signal may be downconverted to an intermediate frequency (IF) and/or to a baseband signal to generate the wideband signal. At least one blocker signal may be bandpass filtered from the amplified input signal.

Abstract: A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.

Abstract: In an envelope comparison embodiment, a delay calibrator produces a delay signal based on a comparison of a feedback signal and an envelope component of the transmitted signal. A down-converter produces the feedback signal from an outgoing modulated RF signal based on at least one local oscillation. Envelope detectors in the delay calibrator and the envelope signal path are operably coupled to a summing node that produces a delay error signal based on a temporal difference between the two envelopes. One embodiment includes phase detectors to detect and adjust the zero crossings of the feedback signal and the envelope signal path. As the delay mismatch between the envelope signal path and the phase signal path increases, the power spectrum increases in adjacent communication channels. A mask margin measurement technique measures the power level in an adjacent channel and adjusts the envelope path delay accordingly.

Abstract: A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the envelope of the translational loop at the translational loop output. The RF transmitter includes an Intermediate Frequency (IF) modulator, a translational loop, an envelope time delay adjust block, an envelope adjust block, and a time delay calibration block. The IF modulator receives a modulated baseband signal and produces a modulated IF signal having a non-constant envelope. The translational loop receives the modulated IF signal and produces a modulated RF signal having a constant envelope. The envelope time delay adjust block receives an envelope signal corresponding to the original modulated signal and produces a time delayed envelope signal based upon a time delay control signal. The envelope adjust block adjusts the modulated RF signal based upon the time delayed envelope signal to produce an envelope adjusted modulated RF signal.

Abstract: A calibration circuit measures the variation in a filter resistor within the analog domain of the envelope path of a polar transmitter and produces a digital value representative of that variation. A digital processor determines a digital control signal from the digital value that is used to compensate, in the digital domain of the envelope path, for the variation in the filter resistor in the analog domain.

Abstract: A polar transmitter includes a digital processor coupled to receive a complex modulated digital signal and a feedback signal produced from the complex modulated digital signal and that is operable to compare the complex modulated digital signal to the feedback signal to determine an error signal indicative of a difference between the complex modulated digital signal and the feedback signal. The digital processor is further operable to produce a correction signal from the error signal and to add the correction signal to the complex modulated digital signal to produce a corrected complex modulated digital signal.

Abstract: A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop.

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

Abstract: A demodulator for use in a receiver converts a digital baseband signal into inbound digital symbols with reduced hardware complexity and reduced power consumption. The demodulator includes a lowpass filter operably coupled to filter the digital baseband signal to produce a filtered digital baseband signal, and an equalizer operating at a first sampling rate to equalize the frequency response of the digital baseband signal such that the receiver overall in-band frequency response approximates the frequency response of a square root raised cosine filter to produce an adjusted digital baseband signal. An interpolator receives the adjusted digital baseband signal at the first sampling rate and interpolates the adjusted digital baseband signal to produce an interpolated digital baseband signal at a second sampling rate, from which the inbound digital symbols can be generated.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: A digital modulator in a radio transmitter includes circuitry for switching between Gaussian Minimum Shift Keying (GMSK) and Phase-Shift Keying (PSK) while maintaining spectral mask requirements. The digital modulator of the present invention includes both GMSK and PSK symbol mappers that produce PSK in-phase and quadrature symbols and GMSK symbols, respectively, to a pulse shaping block. Based on opposite phases of a modulation control signal, the symbol mappers produce either modulated data or a steam of logic zeros to the pulse shaping block. The pulse shaping block filters the received data and multiplexes the data so that each modulated data stream receives non-zero data during a guard time to avoid abrupt changes in the modulated signal that would violate the spectral mask requirements.

Abstract: A polar transmitter includes a digital processor coupled to receive a complex modulated digital signal and a feedback signal produced from the complex modulated digital signal and that is operable to compare the complex modulated digital signal to the feedback signal to determine an error signal indicative of a difference between the complex modulated digital signal and the feedback signal. The digital processor is further operable to produce a correction signal from the error signal and to add the correction signal to the complex modulated digital signal to produce a corrected complex modulated digital signal.

Abstract: A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.

Abstract: A polar transmitter includes a digital processor coupled to receive a complex modulated digital signal and a feedback signal produced from the complex modulated digital signal and that is operable to compare the complex modulated digital signal to the feedback signal to determine an error signal indicative of a difference between the complex modulated digital signal and the feedback signal. The digital processor is further operable to produce a correction signal from the error signal and to add the correction signal to the complex modulated digital signal to produce a corrected complex modulated digital signal.

Abstract: A frequency synthesizer for use in a transmitter operates to receive outbound transmit data and to modulate the outbound transmit data to produce a modulated RF signal. The modulated RF signal can then be amplified to produce an outbound RF signal.

Abstract: A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.