Abstract: A communication device used for near filed communications (NFC). The device includes circuitry that generates a differential signal for communication with an analog front end of the device. The analog front end includes an impedance matching network and an antenna. The antenna is disposed at a predetermined distance away from the boundary of a battery compartment. The antenna forms a single loop around the battery compartment and is coupled to the matching network either in a differential manner or a single ended manner. The communication device includes a protective back casing that is either metallic or plastic in nature. With the single loop antenna configuration, both types of back covers enable efficient NFC.

Abstract: A communication device used for near filed communications (NFC). The device includes circuitry that generates a differential signal for communication with an analog front end of the device. The analog front end includes an impedance matching network and an antenna. The antenna is disposed at a predetermined distance away from the boundary of a battery compartment. The antenna forms a single loop around the battery compartment and is coupled to the matching network either in a differential manner or a single ended manner. The communication device includes a protective back casing that is either metallic or plastic in nature. With the single loop antenna configuration, both types of back covers enable efficient NFC.

Abstract: An antenna section includes a bracket antenna configured to send and receive RF communications of a mobile communication device having a back side that is enclosed by a back cover, wherein the bracket antenna forms a structural portion of the back cover of the mobile communication device that encloses at least one portion of an edge of the mobile communication device and at least one portion of the back side. A booster plate is coupled to the mobile communication device and is configured to electromagnetically interact with the bracket antenna to modify the antenna beam pattern.

Abstract: A method of communicating data in a Bluetooth™ low energy (BLE) module is provided. The method includes modulating an outbound communication signal into a modulated signal with a particular modulation scheme based on a modulation type, and transmitting the modulated signal to a remote device via a wireless communication connection associated with the modulation type. The method also includes receiving an inbound radio frequency (RF) signal, determining if the inbound RF signal is associated with a modulation type, and demodulating the inbound RF signal with a particular modulation scheme based on the modulation type if the inbound RF signal is determined to be associated with a modulation type. In some aspects, the inbound RF signal and outbound modulated signal have symbol rates of 2 Megasymbols per second. In some implementations, the method includes switching between a legacy BLE system and an enhanced rate BLE system.

Abstract: Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (??) phase/frequency detector (?? PFD). A hybrid 2nd-order ?? PFD may be implemented based on a continuous-time 1st-order ?? analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the ?? PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced ?? quantization noise. The implementation of low complexity ?? PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency hands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract: A communication device includes a first and second near-field wireless (NFW) module operating with a first and second protocol, respectively. A module and method to improve the operational efficiency of the first and second NFW modules are disclosed. Due to close proximity between the first and second NFW modules in the communication device, an undesirable parasitic inductive coupling can occur that can degrade the operational performance of the modules. The first NFW module can be configured to control inductive coupling of the second NFW module when an electromagnetic (EM) field operating with the first protocol is detected. Additionally, the second NFW module can be configured to control inductive coupling of the first NFW module when an EM field operating with the second protocol is detected. Controlling the inductive coupling of each module can be performed by means of detuning an inductive coupling element of each module.

Abstract: Techniques and devices are disclosed to provide multi-stage gain control in circuits or devices having two or more stages of signal amplification. A circuit with multi-stage gain control can include amplification stages coupled to receive an input signal and to produce an amplified output signal. Each amplification stage includes an amplifier that is adjustable in gain and a signal detector that is coupled to measure an output signal of the amplifier and to produce a detector signal indicative of a signal strength of the output signal of the amplifier. A gain control circuit is coupled to receive detector signals from the signal detectors in the amplification stages, respectively, and to control gains of the amplifiers of the amplification stages based on respective received detector signals, respectively.

Abstract: A PLL includes independent frequency-locking and phase-locking operational modes. In addition, the PLL includes a hybrid (e.g., mixed-analog/digital signal) 2nd-order delta-sigma (DS) phase/frequency detector. The detector may be implemented based on a continuous-time 1st-order DS Analog to Digital (ADC) converter. The ADC may be enhanced to 2nd-order by using, e.g., closed loop frequency detection. The PLL includes a fine resolution encoder for encoding the DS ADC output. The fine resolution encoding facilitates true multi-bit phase/frequency error digitization with drastically reduced DS quantization noise.

Abstract: Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (??) phase/frequency detector (?? PFD). A hybrid 2nd-order ?? PFD may be implemented based on a continuous-time 1st-order ?? analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the ?? PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced ?? quantization noise. The implementation of low complexity ?? PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).

Abstract: Various embodiments are disclosed relating to power control techniques for wireless transmitters. In an example embodiment, an apparatus is provided that may include a digital-to-analog converter (DAC) adapted to convert a digital amplitude signal to an analog amplitude signal during a first transmission mode and adapted to convert a digital power level signal to an analog power level signal during a second transmission mode.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: A method of communicating data in a Bluetooth™ low energy (BLE) module is provided. The method includes modulating an outbound communication signal into a modulated signal with a particular modulation scheme based on a modulation type, and transmitting the modulated signal to a remote device via a wireless communication connection associated with the modulation type. The method also includes receiving an inbound radio frequency (RF) signal, determining if the inbound RF signal is associated with a modulation type, and demodulating the inbound RF signal with a particular modulation scheme based on the modulation type if the inbound RF signal is determined to be associated with a modulation type. In some aspects, the inbound RF signal and outbound modulated signal have symbol rates of 2 Megasymbols per second. In some implementations, the method includes switching between a legacy BLE system and an enhanced rate BLE system.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency hands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract: Various embodiments are disclosed relating to power control techniques for wireless transmitters. In an example embodiment, an apparatus is provided that may include a digital-to-analog converter (DAC) adapted to convert a digital amplitude signal to an analog amplitude signal during a first transmission mode and adapted to convert a digital power level signal to an analog power level signal during a second transmission mode.

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency bands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.