Abstract: Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal traces and to opposite ends of the piece of silicon using a FIB system. For capacitance, a dielectric is formed on the piece of silicon, and a layer of metal is formed on the dielectric. Vias are formed to regions on the metal traces, to the piece of silicon, and to the layer of metal using the FIB system.

Abstract: A method to de-packaging a semiconductor device to access and test the die within the package. The method involves initially removing molding compound from a first surface of the package to expose the underlying die attach pad of the package. A mask is then formed over the die attach-pad. An etching solution is subsequently introduced through an opening in the mask to etch away the die attach pad. Once the etching is complete, the die attach film is removed. An ohmic contact is then formed on the exposed back surface of the die. The ohmic contact is used to ground the die so that the electrical circuitry on the device will operate properly. Once grounded, the circuitry on the die can be electrically tested and debugged.

Abstract: Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal traces and to opposite ends of the piece of silicon using a FIB system. For capacitance, a dielectric is formed on the piece of silicon, and a layer of metal is formed on the dielectric. Vias are formed to regions on the metal traces, to the piece of silicon, and to the layer of metal using the FIB system.

Abstract: An integrated circuit backside preparation process back-thins a die using a dry etch process. A wet etch process decaps the integrated circuit to expose the die. After polishing, the prepared integrated circuit is ready for a backside debug analysis.