Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: A microscopic hole is produced in a dielectric layer having a dielectric first material, a first surface and a second surface. In one embodiment, the tapered through-hole is etched from the second surface of the layer to the first surface of the layer. The tapered hole provides a first cross section near the first surface of the dielectric layer and a second cross section near the second surface of dielectric layer. A cladding is deposited at the inner surface of the through-hole. The cladding includes a second material and provides a thickness decreasing from the second surface to the first surface.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: A structure in a substrate for the manufacturing of a semiconductor device, wherein a first material and at least one second material are to be etched by at least one etching medium, wherein the at least one second material has a higher etch rate for the at least one etching medium relative to the first material. The at least one second material occupies a space which is at least at one side adjacent to the first material so that an additional etching access to the first material is prepared when at least one etching medium etches the first and the second material.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.

Abstract: A storage capacitor includes a first electrode layer, second electrode layer and a dielectric interlayer arranged between the first electrode layer and the second electrode layer. The dielectric interlayer contains a high-k dielectric and at least one silicon-containing component.

Abstract: Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.

Abstract: Liquid crystalline compounds having a large negative ?? low viscosity, a large K33/K11 value, a small ??/?? and mutually excellent solubility even at low temperature, compositions containing at least one of the compounds and liquid crystal display devices containing such a liquid crystal compositions are disclosed.

Abstract: Atomic layer deposition of very thin dielectric metal oxide layers in manufacturing of semiconductor devices by ozone oxidation of precursor monolayers leads to unacceptable impurity content and leakage current of the layers. It is proposed to perform precursor oxidation by means of radicals generated by oxidizing and reductive gases, which are simultaneously fed into the reaction vessel. This way very low impurity content and leakage current is achieved even in very thin (several nm) layers.

Abstract: A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer.

Abstract: A process is described for depositing silicon nitride, in which the temperature in a furnace is set to from 600° C. to 645° C. The silicon nitride formed in this way is permeable to small molecules, such as in particular hydrogen molecules, yet nevertheless retains its etching selectivity with respect to silicon dioxide.

Abstract: A heating system, a method for heating a deposition reactor or an oxidation reactor, and a reactor utilizing the heating system are particularly suited for low-pressure chemical vapor deposition or oxidation. A heating system is particularly useful for heating a reactor in which a plurality of wafers is held perpendicularly to the reactant gas flowing direction that is parallel to the longitudinal axis of the reactor, to enable a deposition or oxidation reaction. The heating system is adapted to change the reactor temperature during the process. In addition, a method heats a reactor to enable a reaction. Preferably, each of a plurality of reactor zones, into which the reactor is divided in a direction parallel to the reactant gas flowing direction, is heated at a different temperature profile indicating the temperature of this specific zone versus time. Thereby, the in-plane uniformity of deposited or oxidized layers can be largely improved.

Abstract: A heating system, a method for heating a deposition reactor or an oxidation reactor, and a reactor utilizing the heating system are particularly suited for low-pressure chemical vapor deposition or oxidation. A heating system is particularly useful for heating a reactor in which a plurality of wafers is held perpendicularly to the reactant gas flowing direction that is parallel to the longitudinal axis of the reactor, to enable a deposition or oxidation reaction. The heating system is adapted to change the reactor temperature during the process. In addition, a method heats a reactor to enable a reaction. Preferably, each of a plurality of reactor zones, into which the reactor is divided in a direction parallel to the reactant gas flowing direction, is heated at a different temperature profile indicating the temperature of this specific zone versus time. Thereby, the in-plane uniformity of deposited or oxidized layers can be largely improved.

Abstract: There are provided a liquid crystalline compound having a large negative &Dgr;&egr;, low viscosity, a large K33/K11 value, a small &Dgr;&egr;/&egr;L and mutually excellent solubility even at extremely low temperature; a liquid crystal composition prepared from a liquid crystalline compound; and a liquid crystal display device fabricated from such a liquid crystal composition.

Abstract: Liquid crystalline compounds having a large negative &Dgr;∈ low viscosity, a large K33/K11 value, a small &Dgr;∈/&Dgr;⊥ and mutually excellent solubility even at low temperature, compositions containing at least one of the compounds and liquid crystal display devices containing such a liquid crystal compositions are disclosed.