Patents by Inventor Henry Bonges
Henry Bonges has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8635575Abstract: Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.Type: GrantFiled: May 15, 2012Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventor: Henry A. Bonges, III
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Publication number: 20120227025Abstract: Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.Type: ApplicationFiled: May 15, 2012Publication date: September 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Henry A. Bonges, III
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Patent number: 8185859Abstract: Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.Type: GrantFiled: June 15, 2007Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventor: Henry A. Bonges, III
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Patent number: 7941780Abstract: A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.Type: GrantFiled: April 18, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Albrik Avanessian, Henry A. Bonges, III, Dureseti Chidambarrao, Stephen E. Greco, Douglas W. Kemerer, Tina Wagner
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Patent number: 7712057Abstract: A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.Type: GrantFiled: December 13, 2007Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Henry A. Bonges, Terence B. Hook, William F. Pokorny, Jeffrey S. Zimmerman
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Publication number: 20090265673Abstract: A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.Type: ApplicationFiled: April 18, 2008Publication date: October 22, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Albrik Avanessian, Henry A. Bonges, III, Dureseti Chidambarrao, Stephen E. Greco, Douglas W. Kemerer, Tina Wagner
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Publication number: 20090158230Abstract: A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Henry A. Bonges, III, Terence B. Hook, William F. Pokorny, Jeffrey S. Zimmerman
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Publication number: 20070271540Abstract: Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a drain/source of the second FET device are connected to a higher level connector and wherein the higher level connector eliminates a damaging current path between the first element and the second element.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung-Ping Eng, Henry A. Bonges, Jeffrey S. Zimmerman, Terence B. Hook
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Patent number: 7299426Abstract: Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.Type: GrantFiled: May 26, 2005Date of Patent: November 20, 2007Assignee: International Business Machines CorporationInventor: Henry A. Bonges, III
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Publication number: 20070240084Abstract: Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.Type: ApplicationFiled: June 15, 2007Publication date: October 11, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Henry Bonges
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Patent number: 7275226Abstract: A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction values for contact cells can be used to limit the number of neighboring cells which must be explored. In every fourth iteration of the expansion process, corner cells may not be expanded. Reachable areas outside of conductors can also be explored.Type: GrantFiled: April 21, 2004Date of Patent: September 25, 2007Assignee: International Business Machines CorporationInventors: Henry A. Bonges, III, David C. Reynolds, James E. Sundquist
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Publication number: 20060271900Abstract: Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.Type: ApplicationFiled: May 26, 2005Publication date: November 30, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Henry Bonges
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Patent number: 7132318Abstract: Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.Type: GrantFiled: December 4, 2004Date of Patent: November 7, 2006Assignee: International Business Machines CorporationInventors: Henry A. Bonges, III, David L. Harmon, Terence B. Hook, Wing L. Lai
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Patent number: 7120887Abstract: A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.Type: GrantFiled: January 16, 2004Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: Henry A. Bonges, III, Michael S. Gray, Jason D. Hibbeler, Kevin W. McCullen, Robert F. Walker
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Patent number: 7067886Abstract: A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.Type: GrantFiled: November 4, 2003Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Henry A. Bonges, III, David L. Harmon, Terence B. Hook, Wing L. Lai
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Publication number: 20050240886Abstract: A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction values for contact cells can be used to limit the number of neighboring cells which must be explored. In every fourth iteration of the expansion process, corner cells may not be expanded. Reachable areas outside of conductors can also be explored.Type: ApplicationFiled: April 21, 2004Publication date: October 27, 2005Applicant: International Business Machines CorporationInventors: Henry Bonges, David Reynolds, James Sundquist
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Publication number: 20050160390Abstract: A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.Type: ApplicationFiled: January 16, 2004Publication date: July 21, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Henry Bonges, Michael Gray, Jason Hibbeler, Kevin McCullen, Robert Walker
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Publication number: 20050098799Abstract: Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.Type: ApplicationFiled: December 4, 2004Publication date: May 12, 2005Inventors: Henry Bonges, David Harmon, Terence Hook, Wing Lai
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Publication number: 20050093072Abstract: A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Henry Bonges, David Harmon, Terence Hook, Wing Lai
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Patent number: 5313424Abstract: A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.Type: GrantFiled: March 17, 1992Date of Patent: May 17, 1994Assignee: International Business Machines CorporationInventors: Robert D. Adams, Henry A. Bonges, III, James W. Dawson, Erik L. Hedberg