Patents by Inventor Henry C. Yu

Henry C. Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896119
    Abstract: An input-output circuit is coupled to a plurality of serial communication paths and to a physical point-to-point interface. The input-output circuit is configured to transmit data received on the plurality of serial communication paths over the physical point-to-point interface. An application circuit is coupled to the input-output circuit and is configured to communicate via a first one of the paths in performing application functions. A bridge circuit is coupled to the input-output circuit and is configured to communicate via a second one of the paths. A debug circuit is coupled to the application circuit and to the bridge circuit. The debug circuit is configured to capture debug data of the application circuit and provide the debug data to the bridge circuit for communication via the second one of the paths.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 19, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Felix Burton, Henry C. Yu
  • Patent number: 6480990
    Abstract: An application specific integrated circuit (ASIC) and method of manufacture. The ASIC includes a substrate layer, at least one metal layer and an operational block. The metal layer is formed above the substrate layer. The operational block is formed in the substrate layer and the metal layer, and is definable by a two-dimensional boundary. The operational block includes a plurality of operational logic gates, a first subgroup of spare logic gates, a second subgroup of spare logic gates, operational wiring and spare gate wiring. The operational logic gates, the first subgroup and the second subgroup are formed on the substrate layer, with the first subgroup being spaced from the second subgroup. The operational wiring is routed into the metal layer and interconnects the operational logic gates to configure the operational block to perform a desired operation. The spare gate wiring is similarly routed into the metal layer.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: November 12, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Nolan David Sharp, Henry C. Yu