Abstract: Systems and methods for data traffic management in a node in a data network. A data path element receives data packets from the network and receives instructions from a buffer management element, coupled to the data path element, whether specific data packets are to be accepted for buffering or not. This decision is based on the status of a buffer memory bank coupled to the data path element. If a data packet is accepted, a data unit descriptor for that packet is queued for processing by a scheduler element coupled to the data path element. The scheduler element determines when a specific data packet is to be dispatched from the buffer memory bank based on the queued data unit descriptor.

Abstract: Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size.

Abstract: A data traffic management system that has the capability of writing data to the buffer memory at twice its normal rate. The data traffic management system uses a pointer structure that can reference either a single or a dual segment memory bank. A dual segment memory bank enhances the write capability of the data traffic management system by allowing two segments to be simultaneously written to both segment memory banks, with one segment being written to each bank. A pointer data structure with a single/dual indicator (S/D indicator) is used for referencing the memory banks. If the S/D indicator has a D entry, then a dual segment memory bank is addressed. The S/D indicator will have an S entry if a single segment memory bank is addressed. Based on the contents of the S/D indicator, either a single fixed size data segment is written to a single memory bank or two fixed size data segments are written to a dual segment memory bank.

Abstract: A communication system is provided for transmitting and receiving data cells containing control messaging and customer data, including a real-time development system (RDS) and means for generating a plurality of RDS events and RDS commands at predetermined locations within the communication system. Each of the RDS events having an event identifier and a variable length sequence of data bytes for defining the event. Each of the RDS commands having a command identifier and a variable length identifier for defining the command. The communication system also includes means for transmitting the RDS events and RDS commands as data cells throughout the communication system via identical communication links. The communication system also having means located throughout the communication system for selectively filtering the RDS events and RDS commands from the control messaging data and customer data.

Abstract: A communication system is disclosed having a hub slot adapted to receive any one of a plurality of hub cards for receiving and transmitting data cells; a plurality of universal card slots; a plurality of interface cards insertable into any one of said plurality of universal card slots for receiving incoming ones of said data cells containing data and transmitting outgoing ones of said data cells containing data; an add bus having respective data links connected between individual ones of said universal card slots and said hub slot for receiving said outgoing ones of said data cells from said plurality of interface cards and transmitting said outgoing ones of said data cells to said hub slot; a drop bus having a single data link connected between all of said universal card slots and said hub slot for transmitting said incoming ones of said data cells from said hub slot to said plurality of interface cards; and means within each of said interface cards for filtering said incoming ones of said data cells from sa

Abstract: A communication system comprising a hub slot adapted to receive any one of a plurality of hub cards for receiving and transmitting data cells; a plurality of universal card slots; a plurality of interface cards insertable in any one of the plurality of universal card slots for receiving incoming ones of the data cells containing data and transmitting outgoing ones of the data cells containing data; an add bus having respective data links connected between individual ones of the universal card slots and the hub slot for receiving the outgoing ones of the data cells from the plurality of interface cards and transmitting the outgoing ones of the data cells to the hub slot; a drop bus having a single data link connected between all of the universal card slots and the hub slot for transmitting the incoming ones of the data cells from the hub slot to the plurality of interface cards; and an arrangement within each of the interface cards for filtering the incoming ones of the data cells from the drop bus and thereby