Abstract: Test verification code generation may be automated. Automating the generation of the test verification code may include generating an integrated circuit design for an integrated circuit that includes the object model and generating the verification code based on the object model. The object model is used by a parser to generate a verification code. The object model may include field values including a protection parameter field and a sequence field. The protection parameter field may include information that identifies node(s) that are associated with an intended protected region in the integrated circuit design and indicates characteristics of an encoding scheme applied in the intended protected region. The sequence field may include information representing a list of signals that can report an error. The verification code may be configured to inject the error during simulation of the integrated circuit design to verify that the system correctly responds to the error.

Abstract: A method and apparatus for a speculative request indicator is described. A method includes providing, for a cache hierarchy, a messaging protocol used for transfer operations among agents in the cache hierarchy, the messaging protocol indicating acceptable cache coherency states for a cache block indicated in a request message and providing, in the messaging protocol for selection by an agent, a speculative request indicator when sending the request message, wherein the speculative request indicator differentiates between a demand request and a speculative request with respect to the cache block.

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

Abstract: A method for managing orders of operations between one or more clients and one or more servers is disclosed. The method includes partitioning addressable regions of logical servers on or within an interconnect link into multiple regions including a first orderable region, and providing logical client an ability to push ordering responsibility within the first orderable region to a server. Over the first orderable region, two request messages for access to memory-mapped sources including two respective operations are transmitted, and the two request messages originate from a same logical client. The ordering responsibility can include a first rule for order of operations between the two request messages.

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

Abstract: Disclosed are systems and methods that include accessing design parameters to configure an integrated circuit design. The integrated circuit design may include a transaction source or processing node to be included in an integrated circuit. The transaction source or processing node may be configured to transmit memory transactions to memory addresses. A compiler may compile the integrated circuit design with the transaction source or processing node to generate a design output. The design output may be configured to route memory transactions based on their targeting cacheable or non-cacheable memory addresses. The design output may be used to manufacture an integrated circuit.

Abstract: Disclosed are systems and methods that include integrated circuit generation with composable interconnect. In some implementations, a system may access a design parameters data structure that specifies an interconnect topology to be included in an integrated circuit. The system may invoke an integrated circuit design generator that applies the design parameters data structure, including with the interconnect topology. In some implementations, the design parameters data structure may specify a definition for a hardware object (e.g., the interconnect topology) and instances of the hardware object. The definition and the instances may each be modifiable. The system may invoke the generator to apply the design parameters data structure to generate the design.

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

Abstract: A system may provide a placeholder for a component in a block of a first-level integrated circuit design without wiring at least one port of the component. The system may determine a mapping to a provider interface in the block. The system may invoke an integrated circuit generator to generate a second-level integrated circuit design based on the first-level integrated circuit design. The generator when executed replaces the provider interface with the component including wiring ports of the component, including the at least one port, in the second-level integrated circuit design according to the mapping. In some implementations, an application program interface may enable a provider to communicate with the generator. The provider can utilize the API to instantiate the provider interface and determine the mapping.

Abstract: A method and apparatus for a speculative request indicator is described. A method includes providing, for a cache hierarchy, a messaging protocol used for transfer operations among agents in the cache hierarchy, the messaging protocol indicating acceptable cache coherency states for a cache block indicated in a request message and providing, in the messaging protocol for selection by an agent, a speculative request indicator when sending the request message, wherein the speculative request indicator differentiates between a demand request and a speculative request with respect to the cache block.

Abstract: A method and apparatus for a cache coherency state request vector is described. A method includes selecting, by a first agent, one or more bits in a cache coherency state request vector, where a selected bit in the cache coherency state request vector indicates an acceptable cache coherency state for a cache block indicated in a request message, transmitting, by the first agent to a second agent, the request message for the cache block, the request message including the cache coherency state request vector, and receiving, by the first agent from the second agent, a response message with a cache coherency response state, wherein the cache coherency response state indicates a cache coherency state responsive to the cache coherency state request vector.

Abstract: A method for managing orders of operations between one or more clients and one or more servers is disclosed. The method includes partitioning addressable regions of logical servers on or within an interconnect link into multiple regions including a first orderable region, and providing logical client an ability to push ordering responsibility within the first orderable region to a server. Over the first orderable region, two request messages for access to memory-mapped sources including two respective operations are transmitted, and the two request messages originate from a same logical client. The ordering responsibility can include a first rule for order of operations between the two request messages.

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

Abstract: A beverage container. The container includes an inner canister. The inner cannister includes a base coupled to a wall. The wall includes a first wall region and a second wall region adjoining the first wall region. The base and the wall forms an interior region for containing a beverage. The container also includes a lid configured to be removably coupled to the inner canister via a screw mechanism. The lid includes one or more lid magnets. The system also includes an outer sleeve configured to be removably coupled to the inner canister. The outer sleeve includes one or more sleeve magnets. The lids magnets are configured to magnetically couple with the sleeve magnets such that the lid is magnetically stuck to the sleeve and appears to levitate adjacent to the sleeve when the lid magnets come within close proximity to the sleeve magnets.

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: A translating actuator acting between two extreme positions defined by mechanical stops is described. Said actuator comprises: an armature mass movable relative to the armature body, a stiff armature spring set such that the natural resting position of the armature mass is close to the centre of travel between the two extreme positions and pair of latches with sufficient holding force that the armature mass can be held at either extreme position against the restoring force of the spring and can be released quickly relative to the natural period of vibration determined by the armature mass on the armature spring.