Patents by Inventor Henry Cook
Henry Cook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922101Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: March 20, 2023Date of Patent: March 5, 2024Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Publication number: 20230399151Abstract: A beverage container. The container includes an inner canister. The inner cannister includes a base coupled to a wall. The wall includes a first wall region and a second wall region adjoining the first wall region. The base and the wall forms an interior region for containing a beverage. The container also includes a lid configured to be removably coupled to the inner canister via a screw mechanism. The lid includes one or more lid magnets. The system also includes an outer sleeve configured to be removably coupled to the inner canister. The outer sleeve includes one or more sleeve magnets. The lids magnets are configured to magnetically couple with the sleeve magnets such that the lid is magnetically stuck to the sleeve and appears to levitate adjacent to the sleeve when the lid magnets come within close proximity to the sleeve magnets.Type: ApplicationFiled: June 13, 2023Publication date: December 14, 2023Applicant: Become Current PBCInventors: Alexander Stanfell Boone, Richard Henry Cook, Travis Jay Rosbach
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Publication number: 20230237217Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: March 20, 2023Publication date: July 27, 2023Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Patent number: 11687455Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.Type: GrantFiled: October 6, 2022Date of Patent: June 27, 2023Assignee: SiFive, Inc.Inventors: John Ingalls, Wesley Waylon Terpstra, Henry Cook
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Patent number: 11675959Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: October 18, 2021Date of Patent: June 13, 2023Assignee: SiFive, Inc.Inventors: Megan Wachs, Henry Cook, Wesley Waylon Terpstra
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Patent number: 11675945Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: May 2, 2022Date of Patent: June 13, 2023Assignee: SiFive, Inc.Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Patent number: 11610036Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: June 28, 2021Date of Patent: March 21, 2023Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Publication number: 20230033550Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.Type: ApplicationFiled: October 6, 2022Publication date: February 2, 2023Inventors: John Ingalls, Wesley Waylon Terpstra, Henry Cook, Leigang Kou
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Publication number: 20230029660Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.Type: ApplicationFiled: October 6, 2022Publication date: February 2, 2023Inventors: John Ingalls, Wesley Waylon Terpstra, Henry Cook
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Patent number: 11467961Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.Type: GrantFiled: May 27, 2021Date of Patent: October 11, 2022Assignee: SiFive, Inc.Inventors: John Ingalls, Wesley Waylon Terpstra, Henry Cook
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Patent number: 11467962Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.Type: GrantFiled: September 2, 2020Date of Patent: October 11, 2022Assignee: SiFive, Inc.Inventors: John Ingalls, Wesley Waylon Terpstra, Henry Cook, Leigang Kou
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Publication number: 20220261522Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Patent number: 11321511Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: January 25, 2021Date of Patent: May 3, 2022Assignee: SiFive, Inc.Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Publication number: 20220066936Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.Type: ApplicationFiled: September 2, 2020Publication date: March 3, 2022Inventors: John Ingalls, Wesley Waylon Terpstra, Henry Cook, Leigang Kou
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Publication number: 20220035987Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: ApplicationFiled: October 18, 2021Publication date: February 3, 2022Inventors: Megan Wachs, Henry Cook, Wesley Waylon Terpstra
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Publication number: 20210365609Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: ApplicationFiled: June 28, 2021Publication date: November 25, 2021Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Patent number: 11151301Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: April 17, 2020Date of Patent: October 19, 2021Assignee: SiFive, Inc.Inventors: Megan Wachs, Henry Cook, Wesley Waylon Terpstra
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Publication number: 20210286724Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Inventors: John Ingalls, Wesley Waylon Terpstra, Henry Cook
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Patent number: 11048838Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.Type: GrantFiled: August 1, 2019Date of Patent: June 29, 2021Assignee: SiFive, Inc.Inventors: Yunsup Lee, Richard Xia, Derek Pappas, Mark Nugent, Henry Cook, Wesley Waylon Terpstra, Pin Hung Chen
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Publication number: 20210173987Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: ApplicationFiled: January 25, 2021Publication date: June 10, 2021Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra