Abstract: An example circuit includes a voltage regulator, a controller, and a chain of switches. The voltage regulator is configured to generate a supply voltage, the supply voltage connected to each switch in the chain of switches, and generate a supply voltage status signal, the supply voltage status signal indicating a status of the supply voltage. The chain of switches includes a first switch configured to switch the supply voltage to a first subcircuit of a plurality of sub circuits based on the supply voltage status signal and one or more second switches configured to switch the supply voltage to one or more respective subcircuits of the plurality of subcircuits.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A monolithic integrated circuit is provided that includes a semiconductor switch, a constant current source, a capacitor, and a load circuit, which has a load capacitance. An output of the semiconductor switch is connected to the load circuit to turn on and off a supply voltage of the load circuit. The capacitor is connected to the output of the semiconductor switch and to a control input of the semiconductor switch. The constant current source can be or is connected to the control input of the semiconductor switch. Also, a use of a semiconductor switch is provided to reduce the leakage current of a load circuit of a monolithic integrated circuit.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A monolithic integrated circuit is provided that includes a semiconductor switch, a constant current source, a capacitor, and a load circuit, which has a load capacitance. An output of the semiconductor switch is connected to the load circuit to turn on and off a supply voltage of the load circuit. The capacitor is connected to the output of the semiconductor switch and to a control input of the semiconductor switch. The constant current source can be or is connected to the control input of the semiconductor switch. Also, a use of a semiconductor switch is provided to reduce the leakage current of a load circuit of a monolithic integrated circuit.

Abstract: A method for adjusting an RC element with a capacitive element with adjustable capacitance, in particular a capacitor, and/or a resistive element with adjustable resistance, in particular an ohmic resistance, is provided. Multiple adjustment cycles are performed, wherein each adjustment cycle sets a standard value for the capacitance of the capacitive element and/or for the resistance of the resistive element, charges the capacitive element for a predefinable charging time, compares a charging voltage to which the capacitive element has been charged during the charging time with a reference voltage. A comparison result is obtained that indicates whether the charging voltage is larger than the reference voltage or vice versa. In addition, the standard value for the capacitance and/or the resistance and/or the charging time for a subsequent adjustment cycle is selected as a function of the comparison result of at least one preceding adjustment cycle.

Abstract: An ATA (Advanced Technology Attachment) controller is provided that comprises at least one parallel port for connecting to at least one ATA compliant storage device, and at least one serial port for connecting to at least one SATA (Serial ATA) compliant storage device. Further, there is a port switching unit provided for switching to at least one of the parallel and serial ports to enable data transfer to and/or from a storage device connected to the port. This enables a software driven reconfiguration making it possible to switch between a mode where the controller behaves like a conventional ATA controller, and a mode where the controller behaves like a conventional SATA controller. A significant amount of hardware may be reused.

Abstract: A frequency synthesizer usable in a wireless communication device is disclosed that may ensure a low phase noise and an improved performance. The frequency synthesizer has a phase locked loop comprising a controllable oscillator generating an output signal with an output frequency that can be adjusted within a predefined frequency range dependent on the value of a first control signal. A phase/frequency detector generates an error signal in response to a phase and/or frequency difference between an input signal generated by frequency dividing said output signal, and a reference signal. A loop filter generates the first control signal based on said error signal and outputs same to the controllable oscillator. A control unit generates a second control signal from the loop filter signal and provides the second control signal to the controllable oscillator, which is arranged for modifying the predefined frequency range based on the second control signal.

Abstract: A combined ATA and SATA controller is provided that comprises a control unit for controlling data transfer to and/or from an ATA compliant parallel storage device and a control unit for controlling data transfer to and/or from an SATA compliant serial storage device. The controller can concurrently perform the data transfer to and/or from the parallel and serial devices. By reusing a significant amount of controller hardware, the combined controller can be realized in a cost effective manner.

Abstract: A frequency synthesizer usable in a wireless communication device is disclosed that may ensure a low phase noise and an improved performance. The frequency synthesizer has a phase locked loop comprising a controllable oscillator generating an output signal with an output frequency that can be adjusted within a predefined frequency range dependent on the value of a first control signal. A phase/frequency detector generates an error signal in response to a phase and/or frequency difference between an input signal generated by frequency dividing said output signal, and a reference signal. A loop filter generates the first control signal based on said error signal and outputs same to the controllable oscillator. A control unit generates a second control signal from the loop filter signal and provides the second control signal to the controllable oscillator, which is arranged for modifying the predefined frequency range based on the second control signal.

Abstract: A combined ATA and SATA controller is provided that comprises a control unit for controlling data transfer to and/or from an ATA compliant parallel storage device and a control unit for controlling data transfer to and/or from an SATA compliant serial storage device. The controller can concurrently perform the data transfer to and/or from the parallel and serial devices. By reusing a significant amount of controller hardware, the combined controller can be realized in a cost effective manner.

Abstract: An ATA (Advanced Technology Attachment) controller is provided that comprises at least one parallel port for connecting to at least one ATA compliant storage device, and at least one serial port for connecting to at least one SATA (Serial ATA) compliant storage device. Further, there is a port switching unit provided for switching to at least one of the parallel and serial ports to enable data transfer to and/or from a storage device connected to the port. This enables a software driven reconfiguration making it possible to switch between a mode where the controller behaves like a conventional ATA controller, and a mode where the controller behaves like a conventional SATA controller. A significant amount of hardware may be reused.

Abstract: A circuit comprises an active filter with linear elements and a tuning circuit with linear elements of the same type as the filter circuit. A backward counter generates a count value that represents a time constant of the tuning circuit. The initial value of the backward counter contains information concerning the relationship between the time constant of the filter circuit and the tuning circuit. A decoder creates a digital code responsive to the count value which is used to switch an array of linear elements in order to tune the time constant of the filter to approximately a desired design value.

Abstract: A circuit comprises an active filter with linear elements and a tuning circuit with linear elements of the same type as the filter circuit. A backward counter generates a count value that represents a time constant of the tuning circuit. The initial value of the backward counter contains information concerning the relationship between the time constant of the filter circuit and the tuning circuit. A decoder creates a digital code responsive to the count value which is used to switch an array of linear elements in order to tune the time constant of the filter to approximately a desired design value.