Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

Abstract: A software development-based compilation flow for circuit design may include executing, using a processor, a makefile including a plurality of rules for hardware implementation. Responsive to executing a first rule of the plurality of rules, a source file including a kernel specified in a high level programming language may be selected; and, an intermediate file specifying a register transfer level implementation of the kernel may be generated using the processor. Responsive to executing a second rule of the plurality of rules, a configuration bitstream for a target integrated circuit may be generated from the intermediate file using the processor. The configuration bitstream includes a compute unit circuit implementation of the kernel.

Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

Abstract: OpenCL program compilation may include generating, using a processor, a register transfer level (RTL) description of a first kernel of a heterogeneous, multiprocessor design and integrating the RTL description of the first kernel with a base platform circuit design. The base platform circuit design provides a static interface within a programmable integrated circuit to a host of the heterogeneous, multiprocessor design. A first configuration bitstream may be generated from the RTL description of the first kernel using the processor. The first configuration bitstream specifies a hardware implementation of the first kernel and supporting data for the configuration bitstream. The first configuration bitstream and the supporting data may be included within a binary container.

Abstract: Approaches for communicating data from a source device to a target device. In one approach, a communicated data value is segmented into a plurality of data chunks at the source device. A sequence of interrupt transactions is transmitted from the source device to a system bus. The transmitting of each interrupt transaction in the sequence includes transmitting a target identifier on an address bus of the system bus, and the target identifier of each interrupt transaction in the sequence includes a respective one of the data chunks. The sequence of interrupt transactions from the system bus is received at the target device. The communicated data value is reassembled at the target device from the data chunks in the target identifier of the interrupt transactions in the sequence.

Abstract: Within a system comprising a programmable integrated circuit (IC), a method can include storing a first configuration within the system in a read-only memory that is independent of the programmable IC. The programmable IC, being loaded with the first configuration, comprises a circuit that accesses a data source external to the system over a communication link. A second configuration can be downloaded by the programmable IC from the data source. The second configuration can be stored within a random access memory within the system that is independent of the programmable IC. Responsive to a reconfiguration event, the programmable IC can be loaded with the second configuration from the random access memory.

Abstract: Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with first data; executing a first iteration of the system to process the first data; partially reconfiguring the PLD, during execution of the first iteration, to initialize shadow memory elements in the PLD with second data, the shadow memory elements respectively shadowing the memory elements in the system; transferring the second data from the shadow memory elements to the memory elements; and executing a second iteration of the system to process the second data.

Abstract: In one embodiment, an output driver is disclosed. The output driver has a first driving device (Q1) that has a first terminal coupled to a bus line terminal, and a second driving device (Q2) that has a first terminal coupled to the bus line terminal. The first driving device (Q1) is configured to couple the bus line terminal to a reference voltage when activated by a first control signal, and the second driving device (Q2) is configured to couple the bus line terminal to a first supply voltage (Vcc) when the second driving device (Q2) is activated by a second control signal. The output driver also has a controller configured to activate the second control signal after the first control signal is deactivated. The second control signal remains active for a first fixed period of time.

Abstract: Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.

Abstract: A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.

Abstract: Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.