Abstract: Use of a control storage device coupled with a central processing unit is locked, during the loading process from the unit to the device, to a would-be user of the device until such loading process is complete as indicated by a so-called "unlock" command received from the central processing unit. An indication of an error or malfunction in the control storage device either during the loading process or thereafter is also provided to the central processing unit.

Abstract: A writeable control store in a data processing system is provided with a dual mode capability. Coupled with the control store in the system is a central processing unit which may provide the next address of the control store's memory dependent upon the mode of the control store. Otherwise, also dependent upon such mode, the control store memory is addressed, dependent upon the results of tests conducted in the central processing unit, by one of at least two alternative addresses. The control words addressed in the writeable control store are used to control the operation of the central processing unit.

Abstract: An adapter includes free running low power clock circuits connected to provide a time of day value accessible by a central processing unit which couples to the adapter through a controller subsystem. The adapter cicuits are constructed on a circuit board which is installed as part of the controller subsystem. The clock circuits are connected to one terminal of a battery power supply whose other terminal connects to an interface connector included within the adapter. Upon installing the adapter board in the subsystem, the battery power supply is connected to provide power for operating the clock circuits. When the adapter is removed from the subsystem, the battery power supply is disconnected, preventing it from discharging. The adapter includes an adapter connector for connecting the output terminal of the battery power supply to enable the battery to be charged or its power level monitored when the adapter circuit board is installed.

Abstract: A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit (CPU) in executing tasks. The real time adapter unit includes a microprocessing section, a timer section, and a module time of day section. The time of day includes circuits which are connected to provide accurate and reliable time of day values. The timer module section includes circuits which are connected to provide variable time intervals. The circuits of both sections are connected to the circuits of the microprocessing section.

Abstract: A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit in executing tasks. The real time adapter unit includes microprocessing circuits and clock circuits. These circuits are connected to provide accurate and reliable time of day values in response to commands from the central processing unit.

Abstract: A data processing unit's request to a data processing device for the transfer of control and processing of an operation in response to an instruction from the unit, is stalled by the device, dependent on the type of instruction, for a period of time, also dependent on the type of instruction, until the device is ready to process such operation. A shift register arrangement is used in the device, which, dependent on the indicia stored therein, which indicia are appropriately loaded in such register dependent on the type of instruction, is used to delay a response to the unit by requesting the unit to make another request to the device to process the operation called for by the instruction.

Abstract: Clock logic for generating multiple clock pulses during a single clock cycle. In response to a signal indicative of a clock cycle, effectively two clock pulses are produced in a relatively short period of time. Such logic, which includes a delay element, causes first a load pulse to be produced thereby enabling the loading of information into, for example, a register. Additionally, and within the same clock cycle as the load pulse and in response to the same signal, an increment pulse is produced to, for example, increment a counting function which may be included in such register.