Abstract: A method and system are provided. The method includes receiving, by a GNSS receiver, a GNSS signal, rotating, by a carrier rotator, samples of the GNSS signal with carrier phase inputs, inverting, by a chip matched filter (CMF), the rotated samples, and generating, by the CMF, an output based on the inverted samples.

Abstract: A method and system are provided. The method includes receiving, by a GNSS receiver, a GNSS signal, rotating, by a carrier rotator, samples of the GNSS signal with carrier phase inputs, inverting, by a chip matched filter (CMF), the rotated samples, and generating, by the CMF, an output based on the inverted samples.

Abstract: A global navigation satellite system (GNSS) receiver is provided. The GNSS receiver includes a front end processor (FEP) including a low power signaling path and a high power signaling path; an individual GNSS satellite processing (IGSP) module including a low power signaling path and a high power signaling path; and a module programmed to detect a carrier-to-noise density (C/No) of a signal received at the GNSS receiver and select at least one of the low power signaling path and the high power signaling path of the FEP and IGSP module based on the detected C/No.

Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

Abstract: A global navigation satellite system (GNSS) receiver is provided. The GNSS receiver includes a front end processor (FEP) including a low power signaling path and a high power signaling path; an individual GNSS satellite processing (IGSP) module including a low power signaling path and a high power signaling path; and a module programmed to detect a carrier-to-noise density (C/No) of a signal received at the GNSS receiver and select at least one of the low power signaling path and the high power signaling path of the FEP and IGSP module based on the detected C/No.

Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

Abstract: A receiver capable of receiving a spread spectrum signal and having a crosscorrelator that enables a carrier wave (CW) jamming to be identified, tracked, replicated and removed from the received spread spectrum signal after demodulation of a weak signal has occurred.

Abstract: A method and system for dynamic memory allocation and sharing in electronic systems. Embodiments include multi-channel signal processing, including continuously receiving multiple channels, wherein each channel comprises a discrete signal, and processing the multiple channels in a signal processing component on a time-multiplexed basis. Processing the multiple channels includes configuring the signal processing component for one of a plurality of operational modes, including allocating a memory into areas for storage of types of data, wherein certain areas are accessed by certain signal processing subsystems in certain manners. Configuring includes configuring the signal processing component to operate in different modes concurrently for different channels.

Abstract: A signal processing system control method and apparatus are described. Various embodiments include a signal processing system with multiple subsystems. A method for controlling the signal processing system includes storing channel records in a designated area of shared memory. Channel records include channel data that include one of multiple discrete signals to be processed by multiple subsystems in a time-multiplexed manner. The channel record includes information used by the multiple subsystems to process a channel, including information used to configure the multiple subsystems, information used to allocate the shared memory, and information used to communicate between multiple subsystems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window, The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Abstract: A signal processing system control method and apparatus are described. Various embodiments include a signal processing system with multiple subsystems. A method for controlling the signal processing system includes storing channel records in a designated area of shared memory. A channel records include channel data which includes one of multiple discrete signals to be processed by multiple subsystems in a time-multiplexed manner. The channel record includes information used by the multiple subsystems to process a channel, including information used to configure the multiple subsystems, information used to allocate the shared memory, and information used to communicate between multiple subsystems.

Abstract: A receiver capable of receiving a spread spectrum signal and having a crosscorrelator that enables a carrier wave (CW) jamming to be identified, tracked, replicated and removed from the received spread spectrum signal after demodulation of a weak signal has occurred.

Abstract: A method and system for dynamic memory allocation and sharing in electronic systems. Embodiments include multi-channel signal processing, including continuously receiving multiple channels, wherein each channel comprises a discrete signal, and processing the multiple channels in a signal processing component on a time-multiplexed basis. Processing the multiple channels includes configuring the signal processing component for one of a plurality of operational modes, including allocating a memory into areas for storage of types of data, wherein certain areas are accessed by certain signal processing subsystems in certain manners. Configuring includes configuring the signal processing component to operate in different modes concurrently for different channels.