Abstract: A system for multiplying a first multibit digital number by a second multibit digital number to produce a multibit product is disclosed. The system utilizes a plurality of identically programmed digital memories. The memories are selectively interconnected to form a plurality of arrays. The memory comprising the first array receives as an address input the two least significant bits of each of first and second digital numbers to be multiplied and produces as an output the two least significant bits of the product and the carry signals to the next array. The memories comprising the second and subsequent arrays receive as address inputs bits of the first and second digital numbers and the carry signals from the preceding array and produce as an output two additional bits of the product and carry signals to the next array. This process is repeated to produce a product having twice as many bits as the multibit input signals.