Abstract: A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.

Abstract: A switching rectifier circuit includes a pulse width modulation controller, a voltage switching circuit, a pulse width modulation comparator, an error amplifier, a voltage reference, a high threshold voltage comparator and a low threshold voltage comparator. A varying output voltage of the voltage regulator is sampled and compared to a high threshold voltage reference and a low threshold voltage reference. When the sampled output voltage is equal to or greater than the high threshold voltage reference the output voltage is decreased. When the sampled output voltage is equal to or less than the low threshold voltage reference the output voltage is increased.

Abstract: The systems and methods described herein may be used to recommend and provide real time information consumers, in accordance with various embodiments. The systems and methods may comprise operations performed by an information kiosk in electrical communication with other components.

Abstract: A system and method of providing an analog make before break circuit includes a first transistor coupled in series with a second transistor, the first transistor being configured for conducting a high portion of an input signal, the second transistor being configured for conducting a low portion of the input signal. A third transistor is configured to interrupt a connection between the input signal and a first transistor input node, the third transistor having a third transistor threshold voltage between of about 90 and about 110 percent of a second transistor threshold voltage. A fourth transistor is configured to interrupt a connection between the input signal and a second transistor input node, the fourth transistor having a fourth transistor threshold voltage of between about 90 and about 110 percent of a first transistor threshold voltage.

Abstract: A switching rectifier circuit includes a pulse width modulation controller, a voltage switching circuit, a pulse width modulation comparator, an error amplifier, a voltage reference, a high threshold voltage comparator and a low threshold voltage comparator. A varying output voltage of the voltage regulator is sampled and compared to a high threshold voltage reference and a low threshold voltage reference. When the sampled output voltage is equal to or greater than the high threshold voltage reference the output voltage is decreased. When the sampled output voltage is equal to or less than the low threshold voltage reference the output voltage is increased.

Abstract: A soft-start generation system is configured to generate a soft-start voltage. The soft-start generation system includes sawtooth circuitry configured to generate current having a sawtooth waveform and staircase circuitry configured to generate current having an ascending staircase waveform. A ramp-up current may be generated that is a combination of the sawtooth current and the staircase current. The ramp-up current may continuously ramp up to a predetermined current level. The soft-start voltage may be generated based on the ramp-up current.

Abstract: A system and method of providing an analog make before break circuit includes a first transistor coupled in series with a second transistor, the first transistor being configured for conducting a high portion of an input signal, the second transistor being configured for conducting a low portion of the input signal. A third transistor is configured to interrupt a connection between the input signal and a first transistor input node, the third transistor having a third transistor threshold voltage between of about 90 and about 110 percent of a second transistor threshold voltage. A fourth transistor is configured to interrupt a connection between the input signal and a second transistor input node, the fourth transistor having a fourth transistor threshold voltage of between about 90 and about 110 percent of a first transistor threshold voltage.

Abstract: A soft-start generation system is configured to generate a soft-start voltage. The soft-start generation system includes sawtooth circuitry configured to generate current having a sawtooth waveform and staircase circuitry configured to generate current having an ascending staircase waveform. A ramp-up current may be generated that is a combination of the sawtooth current and the staircase current. The ramp-up current may continuously ramp up to a predetermined current level. The soft-start voltage may be generated based on the ramp-up current.

Abstract: An electronic circuit may output a slope compensation signal for performance of slope compensation of a current mode switching regulator. The circuit may generate a voltage across a storage device that is supplied to a voltage-to-current converter, which may generate a first current in response to the supplied voltage. Current mirror circuitry may mirror the current and supply the mirrored current to the storage device to generate the voltage. The current mirror circuitry may also mirror the current to generate a second mirrored current, which may be supplied to an output of the electronic circuit. In addition to using the first mirrored current to generate the voltage, the voltage may be generated by pulling down the voltage to ground in accordance with a duty cycle of a switching signal used for generation of an output of the current mode switching regulator.

Abstract: Various circuits, including DC/DC converters can include an integrated soft-start circuit. The integrated soft-start circuit includes a PMOS transistor configured to receive a reference signal and control the current to a bipolar junction transistor when the reference signal is in a first state. First and second NMOS transistors are included in the soft-start circuit, and receive the reference signal to turn off (to release from reset) when the reference signal is in the first state. A capacitor coupled in parallel with one of the NMOS transistors controls the soft-start signal. Various different transistors types can be used depending on the desired implementation.

Abstract: A current mode direct current-to-direct current (DC-to-DC) voltage regulator controls its output voltage using a pulse width modulation (PWM) circuit that employs a non-linear compensation ramp. By employing such a PWM circuit, the output voltage can be controlled more robustly over a wider range of operating conditions.

Abstract: A current mode direct current-to-direct current (DC-to-DC) voltage regulator controls its output voltage using a pulse width modulation (PWM) circuit that employs a non-linear compensation ramp. By employing such a PWM circuit, the output voltage can be controlled more robustly over a wider range of operating conditions.

Abstract: Various circuits, including DC/DC converters can include an integrated soft-start circuit. The integrated soft-start circuit includes a PMOS transistor configured to receive a reference signal and control the current to a bipolar junction transistor when the reference signal is in a first state. First and second NMOS transistors are included in the soft-start circuit, and receive the reference signal to turn off (to release from reset) when the reference signal is in the first state. A capacitor coupled in parallel with one of the NMOS transistors controls the soft-start signal. Various different transistors types can be used depending on the desired implementation.