Patents by Inventor Henry Horng-Fei Jyu

Henry Horng-Fei Jyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hybrid system of static analysis and dynamic simulation for circuit design
    Patent number: 6820243
    Abstract: A method and system for simulating a circuit design that includes analog and/or digital circuitry uses a hybrid system of static analysis and dynamic simulation. Once the user's circuit is read in and partitioned into stages, the input vectors are applied. A hybrid vector is used to represent a number of possible signal states, for example, a logic 0 or logic 1, as well as a number of possible signal transitions, for example, a rising signal or a falling signal. The possible combinations of states are enumerated and the network in the stage is solved for all possible combinations. The results from the network solutions for the different combinations are recomposed into the hybrid notation, which is then applied to the next stage.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: November 16, 2004
    Assignee: Nassda Corporation
    Inventors: An-Jui Shey, Henry Horng-Fei Jyu, An-Chang Deng
  • Hybrid system of static analysis and dynamic simulation for circuit design
    Patent number: 6718525
    Abstract: A method and system for simulating a circuit design that includes analog and/or digital circuitry uses a hybrid system of static analysis and dynamic simulation. Once the user's circuit is read in and partitioned into stages, the input vectors are applied. A hybrid vector is used to represent a number of possible signal states, for example, a logic 0 or logic 1, as well as a number of possible signal transitions, for example, a rising signal or a falling signal. The possible combinations of states are enumerated and the network in the stage is solved for all possible combinations. The results from the network solutions for the different combinations are recomposed into the hybrid notation, which is then applied to the next stage.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: April 6, 2004
    Assignee: Nassda Corporation
    Inventors: An-Jui Shey, Henry Horng-Fei Jyu, An-Chang Deng
  • Minimization of circuit delay and power through transistor sizing
    Patent number: 6209122
    Abstract: A method for minimizing signal delay and power consumption is provided. Through combined power simulation and delay analysis, iterative transistor resizing is performed based on a variety of factors including relative delay of associated circuit paths, nodal switching activities and association of transistors in channel-connected sets.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: March 27, 2001
    Assignee: Synopsys, Inc.
    Inventors: Henry Horng-Fei Jyu, An-Chang Deng
  • Minimization of circuit delay and power through transistor sizing
    Patent number: 5880967
    Abstract: A method for minimizing signal delay and power consumption is provided. Through combined power simulation and delay analysis, iterative transistor resizing is performed based on a variety of factors including relative delay of associated circuit paths, nodal switching activities and association of transistors in channel-connected sets.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: March 9, 1999
    Assignee: Synopsys, Inc.
    Inventors: Henry Horng-Fei Jyu, An-Chang Deng