Abstract: A device for controlling the flow of command messages in a network in order to alleviate full queue situations that may result in an overrun of commands. The device comprises a counter circuit for determining the number of buffers available in the command queue and a control circuit for controlling the flow of command frames. The control circuit includes a first and second means for storing and is responsive to a status of the command queue and control logic.

Abstract: A memory controller parity system that detects both even and odd bit errors in memory addresses and global errors in memory data. The parity system detects errors in any memory system employing an address bus or data allocation map. It is effective for applications requiring random memory accesses as well as in blocked-data accesses such as in controller buffer memories for servicing disk file systems and tape storage systems. The controller stores data in memory together with a single appended global parity bit representing (n-1) bits from an n-bit address, thereby detecting both even and odd fixed errors over time. A p-bit identification register can be added to the controller to facilitate detection over time of global data errors arising from data allocation map errors during the data storage period. The single-bit parity scheme is compatible with existing single-bit parity memory systems.