Patents by Inventor Henry K. KOERTZEN

Henry K. KOERTZEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10354611
    Abstract: An apparatus comprises a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL to sample the second output with the first output and to generate a pulse-frequency modulation (PFM) output. A voltage regulator comprises mutually coupled on-die inductors for coupling to a load; a bridge coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising a comparator and a first PDL coupled to the comparator.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 16, 2019
    Assignee: INTEL CORPORATION
    Inventors: Fenardi Thenus, Peng Zou, Raghu Nandan Chepuri, Henry K. Koertzen
  • Publication number: 20170301309
    Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output.
    Type: Application
    Filed: July 3, 2017
    Publication date: October 19, 2017
    Inventors: Fenardi THENUS, Peng ZOU, Raghu Nandan CHEPURI, Henry K. KOERTZEN
  • Patent number: 9711108
    Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Fenardi Thenus, Peng Zou, Raghu Nandan Chepuri, Henry K. Koertzen
  • Publication number: 20160111061
    Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output.
    Type: Application
    Filed: June 10, 2013
    Publication date: April 21, 2016
    Inventors: Fenardi THENUS, Peng ZOU, Raghu Nandan CHEPURI, Henry K. KOERTZEN