Abstract: The invention is directed to a circuit arrangement for rapid sortation or selection of at least three digital values according to rank. In the circuit arrangement, the input channels are directly interconnected via digital comparators or arithmetic logic units. The outputs of the digital comparators or arithmetic logic units are connected to a gate-logic circuit or a ROM table controlling data selectors for the transfer of selected values or a network of data selectors for the sortation of all input values.

Abstract: The invention is directed to methods and circuit arrangements for video-rapid determination of the median of an evaluation window. In a first step, the gray values of one column of the evaluation window are transferred in accordance with their relative rank to window line memories; in a second step, selection circuit arrangements select gray values in parallel from all window line memories according to their rank relative to one another. Only these selected gray values are then processed in subsequent steps by processing circuit arrangements.