Patents by Inventor Henry Kuo
Henry Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190318622Abstract: Embodiments of the present disclosure are directed at an improved license plate recognition (LPR) device for identifying vehicular information. In some embodiments, the LPR device includes a DC power source for electrically powering the unit, one or more cameras, processors (or computers), circuitry, and programs for processing images/video captured by the one or more cameras to extract license plate information and/or perform other suitable image processing functions within the LPR device in situ, wired and wireless communications for linking multiple such camera units to each other and to a central data base. The cameras may include infrared and/or color sensors and LEDs, rolling or global shutters, and optical filters.Type: ApplicationFiled: April 16, 2019Publication date: October 17, 2019Inventors: Catherine Shideler, Nicholas Andrew, David Tooby, Tina Barr, Shawn White, Lee McCarty, Henry Kuo, Robert Batchko, Samuel Robinson, Roderick McAfee, James Jordan, Steve Gieseking
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Patent number: 9041153Abstract: According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.Type: GrantFiled: September 29, 2011Date of Patent: May 26, 2015Assignee: BROADCOM CORPORATIONInventors: Xiangdong Chen, Henry Kuo-Shun Chen, Wei Xia, Bruce Chih-Chieh Shen
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Patent number: 8890288Abstract: According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.Type: GrantFiled: October 11, 2011Date of Patent: November 18, 2014Assignee: Broadcom CorporationInventors: Xiangdong Chen, Henry Kuo-Shun Chen
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Publication number: 20140299964Abstract: A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.Type: ApplicationFiled: April 7, 2014Publication date: October 9, 2014Applicant: Broadcom CorporationInventors: Henry Kuo-Shun CHEN, Guang-Jye Shiau, Akira Ito
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Patent number: 8748277Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.Type: GrantFiled: September 13, 2012Date of Patent: June 10, 2014Assignee: Broadcom CorporationInventors: Xiangdong Chen, Wei Xia, Henry Kuo-Shun Chen
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Patent number: 8717137Abstract: A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.Type: GrantFiled: May 31, 2006Date of Patent: May 6, 2014Assignee: Broadcom CorporationInventors: Henry Kuo-Shun Chen, Guang-Jye Shiau, Akira Ito
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Publication number: 20140084368Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicant: Broadcom CorporationInventors: Akira ITO, Henry Kuo-Shun CHEN
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Patent number: 8659081Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.Type: GrantFiled: September 13, 2012Date of Patent: February 25, 2014Assignee: Broadcom CorporationInventors: Xiangdong Chen, Wei Xia, Henry Kuo-Shun Chen
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Patent number: 8598670Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.Type: GrantFiled: November 10, 2010Date of Patent: December 3, 2013Assignee: Broadcom CorporationInventors: Akira Ito, Henry Kuo-Shun Chen
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Publication number: 20130087886Abstract: According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.Type: ApplicationFiled: October 11, 2011Publication date: April 11, 2013Applicant: BROADCOM CORPORATIONInventors: Xiangdong Chen, Henry Kuo-Shun Chen
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Publication number: 20130082351Abstract: According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.Type: ApplicationFiled: September 29, 2011Publication date: April 4, 2013Applicant: BROADCOM CORPORATIONInventors: Xiangdong Chen, Henry Kuo-Shun Chen, Wei Xia, Bruce Chih-Chieh Shen
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Patent number: 8369073Abstract: A multiple hard drive connection system includes a first backplane, a second backplane, and a card assembly. The first backplane includes a pass-through and a first socket, and couples to a control system such that the first socket is in electrical communication with the control system. The second backplane is adjacent to and spaced apart from the first backplane, includes a second socket aligned with the pass-through, and couples to the control system such that the second socket is in electrical communication with the control system. The card assembly includes a first edge card connected to the first socket and a second edge card extending through the pass-through and connected to the second socket. The card assembly couples to a hard drive such that the hard drive is in electrical communication with the control system via the first backplane, the second backplane, and the card assembly.Type: GrantFiled: September 30, 2010Date of Patent: February 5, 2013Assignee: Western Digital Technologies, Inc.Inventors: Minh N. Trinh, Mostafa Pakzad, Suleyman Attila Yolar, Peter H. Greilach, Henry Kuo, Linh G. Tran
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Publication number: 20130017658Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.Type: ApplicationFiled: September 13, 2012Publication date: January 17, 2013Inventors: Xiangdong Chen, Wei Xia, Henry Kuo-Shun Chen
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Publication number: 20130001687Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.Type: ApplicationFiled: September 13, 2012Publication date: January 3, 2013Applicant: Broadcom CorporationInventors: Xiangdong Chen, Wei Xia, Henry Kuo-Shun Chen
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Patent number: 8269275Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.Type: GrantFiled: October 21, 2009Date of Patent: September 18, 2012Assignee: Broadcom CorporationInventors: Xiangdong Chen, Wei Xia, Henry Kuo-Shun Chen
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Publication number: 20120081851Abstract: A multiple hard drive connection system includes a first backplane, a second backplane, and a card assembly. The first backplane includes a pass-through and a first socket, and couples to a control system such that the first socket is in electrical communication with the control system. The second backplane is adjacent to and spaced apart from the first backplane, includes a second socket aligned with the pass-through, and couples to the control system such that the second socket is in electrical communication with the control system. The card assembly includes a first edge card connected to the first socket and a second edge card extending through the pass-through and connected to the second socket. The card assembly couples to a hard drive such that the hard drive is in electrical communication with the control system via the first backplane, the second backplane, and the card assembly.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: Western Digital Technologies, Inc.Inventors: MINH N. TRINH, MOSTAFA PAKZAD, SULEYMAN ATTILA YOLAR, PETER H. GREILACH, HENRY KUO, LINH G. TRAN
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Patent number: 8089118Abstract: According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region.Type: GrantFiled: June 10, 2009Date of Patent: January 3, 2012Assignee: Broadcom CorporationInventors: Xiangdong Chen, Henry Kuo-Shun Chen, Kent Charles Oertle, Jennifer Chiao
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Patent number: 8048765Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.Type: GrantFiled: August 28, 2009Date of Patent: November 1, 2011Assignee: Broadcom CorporationInventors: Xiangdong Chen, Bruce Chih-Chieh Shen, Henry Kuo-Shun Chen
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Publication number: 20110169079Abstract: According to one embodiment, a semiconductor device having an overlapping multi-well implant comprises an isolation structure formed in a semiconductor body, a first well implant formed in the semiconductor body surrounding the isolation structure, and a second well implant overlapping at least a portion of the first well implant. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise a gate formed over the semiconductor body adjacent to the isolation structure, wherein the first well implant extends a first lateral distance under the gate and the second well implant extends a second lateral distance under the gate, and wherein the first and second lateral distances may be different. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including a power management circuit or a power amplifier.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicant: BROADCOM CORPORATIONInventors: Akira Ito, Henry Kuo-Shun Chen, Bruce Chih-Chieh Shen
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Publication number: 20110089490Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.Type: ApplicationFiled: October 21, 2009Publication date: April 21, 2011Applicant: BROADCOM CORPORATIONInventors: Xiangdong Chen, Wei Xia, Henry Kuo-Shun Chen