Patents by Inventor Henry L. Edwards
Henry L. Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153938Abstract: An integrated circuit includes a first transistor array over a semiconductor substrate and is distributed among a first plurality of first transistor banks. A second transistor array in or over the semiconductor substrate is distributed among a second plurality of second transistor banks. A first one of the first transistor banks is located between a first one and a second one of the second transistor banks, and the second one of the second transistor banks is located between the first one of the first transistor banks and a second one of the first transistor banks. The first transistor array and the second transistor array may be alternately operated to implement a voltage-conversion integrated circuit.Type: ApplicationFiled: December 30, 2022Publication date: May 9, 2024Inventors: Neil Gibson, Jerry L. Doorenbos, Gerald Gradl, VIOLA Schaeffer, Archana Venugopal, Henry L. Edwards
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Publication number: 20230402920Abstract: A switching regulator includes a low-side switching transistor, a snubber transistor, a first pull-down transistor, and a second pull-down transistor. The low-side switching transistor includes a first current terminal and a second current terminal. The first current terminal is coupled to a switching node. The second current terminal is coupled to a ground terminal. The snubber transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to the switching node. The second current terminal is coupled to the ground terminal. The first pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal. The second pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal.Type: ApplicationFiled: May 31, 2022Publication date: December 14, 2023Inventors: Henry L. EDWARDS, Wei DA, Stephen BRINK, Joseph Maurice KHAYAT
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Publication number: 20230108106Abstract: An integrated circuit includes a semiconductor substrate with a semiconductor surface layer having a first conductivity type and a top surface, a diode including a buried region within the surface layer, the buried region having an opposite second conductivity type and being spaced apart from the top surface by a portion of the semiconductor surface layer having the first conductivity type, a dielectric layer over the surface layer, and a metal layer located over the dielectric layer and including an aperture extending laterally in a first direction over the semiconductor surface layer and laterally spaced apart from the buried region in a second direction.Type: ApplicationFiled: June 29, 2022Publication date: April 6, 2023Inventors: Henry L. Edwards, Udumbara Wijesinghe, William R. Krenik
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Patent number: 10930641Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.Type: GrantFiled: December 5, 2018Date of Patent: February 23, 2021Assignee: Texas Instruments IncorporatedInventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
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Patent number: 10573578Abstract: An integrated circuit has thermoelectric cooling devices integrated into bondpads. A method for operating the integrated circuit includes turning a thermal switch to a thermoelectric cooler operate position when the integrated circuit is powered up, turning the thermal switch to a thermoelectric cooler operate position to allow the thermoelectric cooler to operate when the integrated circuit powers down, and turning the thermal switch to a thermoelectric cooler off position when a predetermined integrated circuit chip temperature is reached.Type: GrantFiled: March 13, 2013Date of Patent: February 25, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Henry L. Edwards
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Publication number: 20190109128Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.Type: ApplicationFiled: December 5, 2018Publication date: April 11, 2019Inventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
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Patent number: 10192863Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.Type: GrantFiled: March 21, 2014Date of Patent: January 29, 2019Assignee: Texas Instruments IncorporatedInventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
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Publication number: 20180323361Abstract: A circuit board includes an embedded thermoelectric device with hard thermal bonds. A method includes embedding a thermoelectric device in a circuit board and forming hard thermal bonds.Type: ApplicationFiled: July 10, 2018Publication date: November 8, 2018Inventors: Henry L. Edwards, Kenneth J. Maggio, Steven Kummerl, Sreenivasan K. Koduri
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Patent number: 9997511Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).Type: GrantFiled: November 25, 2015Date of Patent: June 12, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry L. Edwards, Akram A. Salman, Lili Yu
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Patent number: 9899368Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).Type: GrantFiled: November 25, 2015Date of Patent: February 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry L. Edwards, Akram A. Salman, Lili Yu
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Patent number: 9831231Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).Type: GrantFiled: November 25, 2015Date of Patent: November 28, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry L. Edwards, Akram A. Salman, Lili Yu
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Publication number: 20160079750Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
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Publication number: 20160079228Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
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Publication number: 20160079227Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
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Patent number: 9231403Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).Type: GrantFiled: March 24, 2014Date of Patent: January 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry L. Edwards, Akram A. Salman, Lili Yu
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Publication number: 20150270708Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).Type: ApplicationFiled: March 24, 2014Publication date: September 24, 2015Applicant: Texas Instruments IncorporatedInventors: Henry L. Edwards, Akram A. Salman, Lili Yu
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Publication number: 20150270257Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: Texas Instruments IncorporatedInventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
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Patent number: 9000505Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.Type: GrantFiled: August 26, 2011Date of Patent: April 7, 2015Assignee: Texas Instruments IncorporatedInventors: Henry L. Edwards, Tathagata Chatterjee, Robert C. Bowen
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Publication number: 20130255741Abstract: An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger.Type: ApplicationFiled: March 13, 2013Publication date: October 3, 2013Inventors: Henry L. Edwards, Richard B. Irwin, Tathagata Chatterjee
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Patent number: 8362462Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.Type: GrantFiled: February 9, 2011Date of Patent: January 29, 2013Assignee: Texas Instruments IncorporatedInventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee