Patents by Inventor Henry L. Edwards

Henry L. Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930641
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: February 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
  • Patent number: 10573578
    Abstract: An integrated circuit has thermoelectric cooling devices integrated into bondpads. A method for operating the integrated circuit includes turning a thermal switch to a thermoelectric cooler operate position when the integrated circuit is powered up, turning the thermal switch to a thermoelectric cooler operate position to allow the thermoelectric cooler to operate when the integrated circuit powers down, and turning the thermal switch to a thermoelectric cooler off position when a predetermined integrated circuit chip temperature is reached.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Henry L. Edwards
  • Publication number: 20190109128
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Inventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
  • Patent number: 10192863
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: January 29, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
  • Publication number: 20180323361
    Abstract: A circuit board includes an embedded thermoelectric device with hard thermal bonds. A method includes embedding a thermoelectric device in a circuit board and forming hard thermal bonds.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Henry L. Edwards, Kenneth J. Maggio, Steven Kummerl, Sreenivasan K. Koduri
  • Patent number: 9997511
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 12, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Patent number: 9899368
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Patent number: 9831231
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: November 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Publication number: 20160079750
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Publication number: 20160079227
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Publication number: 20160079228
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Patent number: 9231403
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: January 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Publication number: 20150270708
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Publication number: 20150270257
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 24, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
  • Patent number: 9000505
    Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: April 7, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Tathagata Chatterjee, Robert C. Bowen
  • Publication number: 20130255741
    Abstract: An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 3, 2013
    Inventors: Henry L. Edwards, Richard B. Irwin, Tathagata Chatterjee
  • Patent number: 8362462
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: January 29, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Publication number: 20120098590
    Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.
    Type: Application
    Filed: August 26, 2011
    Publication date: April 26, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Tathagata Chatterjee, Robert C. Bowen
  • Publication number: 20110127572
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Application
    Filed: February 9, 2011
    Publication date: June 2, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Patent number: 7943450
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee