Abstract: When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a single clock edge, thereby permitting the passage of the required number of clock pulses for a test. The system uses the functional clock and the clock distribution tree designed into the ASIC.

Abstract: A pipeline array includes a register, a pipeline clock input, and Narrow Pulse Triggered Latches (NPTL) stages connected in series. Each NPTL stage includes a Latch Pulse Generator (LPG) and a parallel set of single latches clocked by the LPG. The latches provide the parallel data input and the parallel data output of the stage. Each LPG provides a narrow latch clock pulse in response to a Pipeline Clock Pulse (PCP) supplied to the register and the last stage of latches. Each PCP arrives at each preceding LPG in the array after a delay provided by intervening time delay units. The delays increase for each preceding stage with the least delay at the penultimate stage and with the greatest delay at the first stage. The data input of the first stage is connected to the output of the register. The data input of the each of other stage is connected to the data output of the preceding stage in the array.

Abstract: A data processing system having a compression and decompression apparatus based on the Lempel-Ziv algorithm. The compression apparatus includes a history RAM unit for receiving and storing one or more data elements and a coding unit for determining whether received data elements previously have been stored in the history RAM unit and are a candidate for compression. If a received data element matches at least one of the stored data elements, an address of the matching stored data element is generated. The compression apparatus generates a compression token comprising an identification of whether a data element is compressed, the length of the coded data within a plurality of predetermined data length categories and an address. The decompression apparatus also includes a history RAM unit for storing received data elements and includes a circuit for receiving a compression token and determining the storage addresses of the next data element from the length and address information contained in the token.