Patents by Inventor Henry Sanford-Crane
Henry Sanford-Crane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10688621Abstract: The polishing pad is suitable for polishing or planarizing at least one of semiconductor, optical and magnetic substrates with a polishing fluid and relative motion between the polishing pad and the at least one of semiconductor, optical and magnetic substrates. The polishing layer has an open-cell polymeric matrix, a polishing surface, a plurality of grooves in the polishing layer. The plurality of projecting land areas are buttressed with a tapered support structure that extends outward and downward from the bottom plurality of projecting land areas. The plurality of projecting land areas have an average width less than average width of the plurality of grooves for decreasing polishing dwell time of the projecting land areas and increasing the debris removal dwell time of the groove areas to a value greater than the polishing dwell time.Type: GrantFiled: August 4, 2016Date of Patent: June 23, 2020Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: Henry Sanford-Crane, Shuiyuan Luo
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Patent number: 10259099Abstract: The method forms a porous polyurethane polishing pad by coagulating thermoplastic polyurethane to create a porous matrix having large pores extending upward from a base surface and open to an upper surface. The large pores are interconnected with small pores. Heating a press to temperature below or above the softening onset temperature of the thermoplastic polyurethane forms a series of pillows. Plastic deforming side walls of the pillow structures forms downwardly sloped side walls. The downwardly sloped side walls extend from all sides of the pillow structures. The large pores open to the downwardly sloped sidewalls are less vertical than the large pores open to the top polishing surface and are offset 10 to 60 degrees from the vertical direction.Type: GrantFiled: August 4, 2016Date of Patent: April 16, 2019Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: Koichi Yoshida, Kazutaka Miyamoto, Katsumasa Kawabata, Henry Sanford-Crane, Hui Bin Huang, George C. Jacob, Shuiyuan Luo
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Patent number: 10106662Abstract: The porous polyurethane polishing pad includes a porous matrix having large pores that extend upward from a base surface and open to an upper surface. The large pores are interconnected with small pores. The porous matrix is a blend of two thermoplastic polymers. The first thermoplastic polyurethane has by molecular percent, 45 to 60 adipic acid, 10 to 30 MDI-ethylene glycol and 15 to 35 MDI and an Mn of 40,000 to 60,000 and a Mw of 125,000 to 175,000 and an Mw to Mn ratio of 2.5 to 4 The second thermoplastic polyurethane has by molecular percent, 40 to 50 adipic acid, 20 to 40 adipic acid butane diol, 5 to 20 MDI-ethylene glycol and 5 to 25 MDI and an Mn of 60,000 to 80,000 and a Mw of 125,000 to 175,000 and an Mw to Mn ratio of 1.5 to 3.Type: GrantFiled: August 4, 2016Date of Patent: October 23, 2018Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: Shuiyuan Luo, George C. Jacob, Henry Sanford-Crane, Koichi Yoshida, Katsumasa Kawabata, Shusuke Kitawaki, Shogo Takahashi, Yosuke Takei
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Patent number: 9925637Abstract: The porous polyurethane polishing pad includes a porous polyurethane matrix having large pores extending upward from a base surface and open to a polishing surface. A series of pillow structures is formed from the porous matrix that include the large pores and the small pores. The pillow structures have a downward surface extending from the top polishing surface for forming downwardly sloped side walls at an angle from 30 to 60 degrees from the polishing surface. The large pores open to the downwardly sloped sidewalls and are less vertical than the large pores. The large pores are offset 10 to 60 degrees from the vertical direction in a direction more orthogonal to the sloped sidewalls.Type: GrantFiled: August 4, 2016Date of Patent: March 27, 2018Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: Koichi Yoshida, Kazutaka Miyamoto, Katsumasa Kawabata, Henry Sanford-Crane, Hui Bin Huang, George C. Jacob, Shuiyuan Luo
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Publication number: 20180037706Abstract: The porous polyurethane polishing pad includes a porous matrix having large pores that extend upward from a base surface and open to an upper surface. The large pores are interconnected with small pores. The porous matrix is a blend of two thermoplastic polymers. The first thermoplastic polyurethane has by molecular percent, 45 to 60 adipic acid, 10 to 30 MDI-ethylene glycol and 15 to 35 MDI and an Mn of 40,000 to 60,000 and a Mw of 125,000 to 175,000 and an Mw to Mn ratio of 2.5 to 4 The second thermoplastic polyurethane has by molecular percent, 40 to 50 adipic acid, 20 to 40 adipic acid butane diol, 5 to 20 MDI-ethylene glycol and 5 to 25 MDI and an Mn of 60,000 to 80,000 and a Mw of 125,000 to 175,000 and an Mw to Mn ratio of 1.5 to 3.Type: ApplicationFiled: August 4, 2016Publication date: February 8, 2018Inventors: Shuiyuan Luo, George C. Jacob, Henry Sanford-Crane, Koichi Yoshida, Katsumasa Kawabata, Shusuke Kitawaki, Shogo Takahashi, Yosuke Takei
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Publication number: 20180036863Abstract: The polishing pad is suitable for polishing or planarizing at least one of semiconductor, optical and magnetic substrates with a polishing fluid and relative motion between the polishing pad and the at least one of semiconductor, optical and magnetic substrates. The polishing layer has an open-cell polymeric matrix, a polishing surface a plurality of grooves in the polishing layer. The plurality of projecting land areas are buttressed with a tapered support structure that extends outward and downward from the bottom plurality of projecting land areas. The plurality of projecting land areas have an average width less than average width of the plurality of grooves for decreasing polishing dwell time of the projecting land areas and increasing the debris removal dwell time of the groove areas to a value greater than the polishing dwell time.Type: ApplicationFiled: August 4, 2016Publication date: February 8, 2018Inventors: Henry Sanford-Crane, Shuiyuan Luo
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Publication number: 20180036862Abstract: The porous polyurethane polishing pad includes a porous polyurethane matrix having large pores extending upward from a base surface and open to a polishing surface. A series of pillow structures is formed from the porous matrix that include the large pores and the small pores. The pillow structures have a downward surface extending from the top polishing surface for forming downwardly sloped side walls at an angle from 30 to 60 degrees from the polishing surface. The large pores open to the downwardly sloped sidewalls and are less vertical than the large pores. The large pores are offset 10 to 60 degrees from the vertical direction in a direction more orthogonal to the sloped sidewalls.Type: ApplicationFiled: August 4, 2016Publication date: February 8, 2018Inventors: Koichi Yoshida, Kazutaka Miyamoto, Katsumasa Kawabata, Henry Sanford-Crane, Hui Bin Huang, George C. Jacob, Shuiyuan Luo
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Publication number: 20180036860Abstract: The method forms a porous polyurethane polishing pad by coagulating thermoplastic polyurethane to create a porous matrix having large pores extending upward from a base surface and open to an upper surface. The large pores are interconnected with small pores. Heating a press to temperature below or above the softening onset temperature of the thermoplastic polyurethane forms a series of pillows. Plastic deforming side walls of the pillow structures forms downwardly sloped side walls. The downwardly sloped side walls extend from all sides of the pillow structures. The large pores open to the downwardly sloped sidewalls are less vertical than the large pores open to the top polishing surface and are offset 10 to 60 degrees from the vertical direction.Type: ApplicationFiled: August 4, 2016Publication date: February 8, 2018Inventors: Koichi Yoshida, Kazutaka Miyamoto, Katsumasa Kawabata, Henry Sanford-Crane, Hui Bin Huang, George C. Jacob, Shuiyuan Luo
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Patent number: 8408977Abstract: The polishing pad is useful for polishing at least one of magnetic, optical and semiconductor substrates. A porous polishing layer includes a dual porosity structure within a polyurethane matrix. The dual porosity structure has a primary set of pores having pore walls with a thickness of 15 to 55 ?m and a storage modulus of 10 to 60 MPa measured at 25° C. In addition, pore walls contain a secondary set of pores having an average pore size of 5 to 30 ?m. The porous polishing layer is either fixed to a polymeric film or sheet substrate or formed into a woven or non-woven structure to form the polishing pad.Type: GrantFiled: March 16, 2012Date of Patent: April 2, 2013Assignee: Rohm and Haas Electronic Materials CMP Inc.Inventors: David B. James, Henry Sanford-Crane
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Publication number: 20120171940Abstract: The polishing pad is useful for polishing at least one of magnetic, optical and semiconductor substrates. A porous polishing layer includes a dual porosity structure within a polyurethane matrix. The dual porosity structure has a primary set of pores having pore walls with a thickness of 15 to 55 ?m and a storage modulus of 10 to 60 MPa measured at 25° C. In addition, pore walls contain a secondary set of pores having an average pore size of 5 to 30 ?m. The porous polishing layer is either fixed to a polymeric film or sheet substrate or formed into a woven or non-woven structure to form the polishing pad.Type: ApplicationFiled: March 16, 2012Publication date: July 5, 2012Applicant: Rohm and Haas Electronic Materials CMP Holdings Inc.Inventors: David B. James, Henry Sanford-Crane
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Patent number: 8162728Abstract: The polishing pad is useful for polishing at least one of magnetic, optical and semiconductor substrates. A porous polishing layer includes a dual porosity structure within a polyurethane matrix. The dual porosity structure has a primary set of pores having pore walls with a thickness of 15 to 55 ?m and a storage modulus of 10 to 60 MPa measured at 25° C. In addition, pore walls contain a secondary set of pores having an average pore size of 5 to 30 ?m. The porous polishing layer is either fixed to a polymeric film or sheet substrate or formed into a woven or non-woven structure to form the polishing pad.Type: GrantFiled: September 28, 2009Date of Patent: April 24, 2012Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: David B. James, Henry Sanford-Crane
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Publication number: 20110076928Abstract: The polishing pad is useful for polishing at least one of magnetic, optical and semiconductor substrates. A porous polishing layer includes a dual porosity structure within a polyurethane matrix. The dual porosity structure has a primary set of pores having pore walls with a thickness of 15 to 55 ?m and a storage modulus of 10 to 60 MPa measured at 25° C. In addition, pore walls contain a secondary set of pores having an average pore size of 5 to 30 ?m. The porous polishing layer is either fixed to a polymeric film or sheet substrate or formed into a woven or non-woven structure to form the polishing pad.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Inventors: David B. James, Henry Sanford-Crane