Abstract: A circuit includes a first transistor M.sub.1 ; a second transistor M.sub.2 having a gate coupled to a gate of the first transistor M.sub.1 and a source coupled to a source of the first transistor M.sub.1 ; a third transistor M.sub.3 having a source coupled to a drain of the first transistor M.sub.1 and a drain coupled to a current input I.sub.b, the drain of the third transistor M.sub.3 is coupled to the gate of the first transistor M.sub.1 ; a fourth transistor M.sub.4 having a source coupled to a drain of the second transistor M.sub.2, a gate coupled to a gate of the third transistor M.sub.3, and a drain coupled to a supply node V.sub.DD ; and a variable voltage input V.sub.x coupled to the gate of the third transistor M.sub.3.

Abstract: A TTL compatible CMOS high-speed lower-power supply-independent input buffer has a first current mirror which supplies current to a reference node of the input buffer when the signal at the input node of the buffer goes to a high state. An MOS transistor has its gate connected to the input node and switches hard on when the input node goes to a high level, pulling the reference node to a low level. A second current mirror is provided which injects current into the reference node for a predetermined period of time after the voltage level at the input of the buffer goes to a low level to pull the reference node to a high level. Both the first and second current mirror are switched on only during transition states of the input buffer, to minimize power dissipation when the input buffer is in its quiescent state.