Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

Abstract: Embodiments of the present disclosure provide stress optimization during manufacturing of dual embedded epitaxially grown (EPI) semiconductor structures using just two masks, such as nFET and pFET open for embedded epitaxial using SiC and SiGe, and separated halo implantation masks for both horizontal and vertical PC

Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.

Abstract: A method of manufacturing dual embedded epitaxially grown semiconductor transistors is provided, the method including depositing a first elongated oxide spacer over first and second transistors of different types, depositing a first elongated nitride spacer on the first oxide spacer, depositing a first photoresist block on the nitride spacer above the first transistor, etching the first nitride spacer above the second transistor, implanting a first halo around the second transistor, etching a first recess in an outer portion of the first halo, stripping the first photoresist above the first transistor, forming a first epitaxially grown semiconductor material in the first recess, implanting a first extension in a top portion of the first material, depositing an elongated blocking oxide over the first and second transistors and first extension, depositing a second photoresist block on the blocking oxide above the second transistor and first extension, etching the blocking oxide and first nitride spacer above th

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

Abstract: Methods of fabricating transistors, semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, and forming a gate over the gate dielectric. Sidewall spacers are formed over the gate dielectric and the gate, the sidewall spacers comprising germanium oxide (GeO or GeO2).

Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first material on the semiconductor wafer, and affecting the semiconductor wafer with a manufacturing process. The manufacturing process inadvertently causes a portion of the first material to be removed. The portion of the first material is replaced with a second material.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.

Abstract: In a method of making a semiconductor device, a recess is formed in an upper surface of the semiconductor body of a first material. An embedded semiconductor region is formed in the recess. The embedded semiconductor region is formed from a second semiconductor material that is different than the first semiconductor material. An upper surface of the embedded semiconductor region is amorphized to create an amorphous region. A silicide is then formed over the amorphous region.

Abstract: A semiconductor structure and its method of fabrication employ a semiconductor substrate having a channel region. A gate electrode is located over the semiconductor substrate. A spacer is located adjacent a sidewall of the gate electrode. The spacer is formed of a material having a modulus of from about 10 to about 50 GPa. The modulus provides enhanced stress within the channel region.

Abstract: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Abstract: Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

Abstract: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

Abstract: The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.