Abstract: A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Abstract: A secure data exchange system permits device to exchange secure message keys and securely transmit messages between devices. The devices may initially exchange temporary message keys that are used to encrypt permanent message keys. In addition, devices may have pairing managed that authenticates devices. Devices may be associated with an address ledger that maintains address information and is accessible with a public ledger key, which may provide different access to address information to different paired devices. Data within the system may also be encrypted with user device keys that prevents unauthorized access to data while permitting recreation of the user device key for data backup and migration.

Abstract: A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Abstract: A secure data exchange system permits device to exchange secure message keys and securely transmit messages between devices. The devices may initially exchange temporary message keys that are used to encrypt permanent message keys. In addition, devices may have pairing managed that authenticates devices. Devices may be associated with an address ledger that maintains address information and is accessible with a public ledger key, which may provide different access to address information to different paired devices. Data within the system may also be encrypted with user device keys that prevents unauthorized access to data while permitting recreation of the user device key for data backup and migration.

Abstract: A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Abstract: A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Abstract: A secure data exchange system permits device to exchange secure message keys and securely transmit messages between devices. The devices may initially exchange temporary message keys that are used to encrypt permanent message keys. In addition, devices may have pairing managed that authenticates devices. Devices may be associated with an address ledger that maintains address information and is accessible with a public ledger key, which may provide different access to address information to different paired devices. Data within the system may also be encrypted with user device keys that prevents unauthorized access to data while permitting recreation of the user device key for data backup and migration.

Abstract: In one aspect, the present invention overcomes the limitations of the prior art by provident a logic simulation ;system that uses a VLIW simulation processor with many parallel processor elements to accelerate the simulation of synthesizable tasks but that also supports non-synthesizable tasks and/or branching. In one approach, the VLIW simulation processor is based on an architecture that does not have an on-chip instruction cache. Instead, VLIW instruction words stream in directly from a program memory and the individual processor elements are programmed continuously based on the instruction words. This also allows the efficient implementation of side-entrance jumps, where a region of code can be entered in the middle of the region rather than always requiring entrance from the top. In another aspect, non-synthesizable tasks can be efficiently handled by exception handlers.

Abstract: A processor system comprising a processor and a memory system with a high data transfer rate and low average power consumption of related I/O activity. The processor system may be disposed on a single circuit board. One embodiment of a disclosed system includes a processor system that comprises a processor device, a memory device and a circuit board. The circuit board includes a substrate, electrical contacts, and interconnection lines between the contacts. The electrical contacts of the circuit board may be coupled to electrical contacts on the processor device and the memory device. The interconnection lines communicate signals, such as data or instructions, between the electrical contacts of the memory device and the process device at least 200 billion bits per second while related input/output activity of the processor and the memory consumes an average power less than ten watts.

Abstract: In one aspect, logic simulation of a design of a semiconductor chip is performed on a domain-by-domain basis (e.g., by clock domain), but storing a history of the state space of the domain during simulation. In this way, additional information beyond just the end result can be reviewed in order to debug or otherwise analyze the design.

Abstract: A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in order to simulate the chip. The storage memory is used to simulate the user memory. Since the program memory and storage memory are separately accessible by the simulation processor, the simulation of reads and writes to user memory does not block the transfer of instructions between the program memory and the simulation processor, thus increasing the speed of simulation. In one aspect, user memory addresses are mapped to storage memory addresses by adding a fixed, predetermined offset to the user memory address. Thus, no address translation is required at run-time.

Abstract: A simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic operation, and a shift register for storing intermediate values generating during the logic simulation. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units can also include one or more bypass multiplexers coupled between the output of the processor element and the interconnect system, for providing a path for bypassing the shift register to provide the output of the processor element directly to the interconnect system.

Abstract: A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic gate, and a shift register associated with the processor element. The shift register includes multiple entries to store the intermediate values, and is coupled to receive the output of the processor element. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units may further include a local memory for storing data from, and loading the data to, the simulation processor.

Abstract: A logic simulation processor uses multi-state logic (e.g., in 4-state, signals may take the values 0, 1, X or Z in the simulation of a semiconductor chip design). Typically a reduced number of basic multi-state logic functions are selected for the instruction set of the processor. Logic functions that are not part of the basic set are simulated by constructing them from combinations of the basic logic functions. In this way, the instruction length remains a manageable size but all logic functions that may occur can be simulated. The basic VLIW architecture can be extended to other applications.