Abstract: A solution for handling objects in a nursery heap that includes a garbage collector monitoring engine, a size adjustor program, and/or a promotion program. The garbage collector monitoring engine can monitor occurrences of global garbage collection events performed by a global garbage collector program as well as occurrences of nursery garbage collection events performed by a nursery garbage collector. The size adjustor program can dynamically adjust a size of a nursery heap based upon programmatically deterministic events detected by the garbage collector monitoring engine. The promotion program can dynamically adjust conditions of promotion for nursery objects, wherein when additional space is needed in the nursery heap to reduce nursery garbage collection induced latency, the promotion program changes promotion criteria to ensure objects are promoted more frequently from the nursery heap.

Abstract: A solution for handling objects in a nursery heap that includes a garbage collector monitoring engine, a size adjustor program, and/or a promotion program. The garbage collector monitoring engine can monitor occurrences of global garbage collection events performed by a global garbage collector program as well as occurrences of nursery garbage collection events performed by a nursery garbage collector. The size adjustor program can dynamically adjust a size of a nursery heap based upon programmatically deterministic events detected by the garbage collector monitoring engine. The promotion program can dynamically adjust conditions of promotion for nursery objects, wherein when additional space is needed in the nursery heap to reduce nursery garbage collection induced latency, the promotion program changes promotion criteria to ensure objects are promoted more frequently from the nursery heap.

Abstract: A mechanism is provided for supporting stack cache memory device management of POP read or PUSH write data in a computer system. The computer system further comprises a main memory and a processor associated with the stack cache memory device. The stack cache memory device includes at least one cache line having a plurality of address spaces arranged from a lowest address to a highest address. In response to the processor initiating a POP read or PUSH write operation, the mechanism provides logic for preventing placement of data in the cache which will not be reused by the processor, and for further preventing removal of data which may be reused by the processor.