Abstract: Apparatus are provided for monitoring a condition of a tissue based on a measurement of an electrical property of the tissue. In an example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least two conductive structures, each having a non-linear configuration, where the at least two conductive structures are disposed substantially parallel to each other. In another example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least one inductor structure.

Abstract: Apparatus are provided for monitoring a condition of a tissue based on a measurement of an electrical property of the tissue. In an example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least two conductive structures, each having a non-linear configuration, where the at least two conductive structures are disposed substantially parallel to each other. In another example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least one inductor structure.

Abstract: Apparatus are provided for monitoring a condition of a tissue based on a measurement of an electrical property of the tissue. In an example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least two conductive structures, each having a non-linear configuration, where the at least two conductive structures are disposed substantially parallel to each other. In another example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least one inductor structure.

Abstract: Apparatus are provided for monitoring a condition of a tissue based on a measurement of an electrical property of the tissue. In an example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least two conductive structures, each having a non-linear configuration, where the at least two conductive structures are disposed substantially parallel to each other. In another example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least one inductor structure.

Abstract: Apparatus are provided for monitoring a condition of a tissue based on a measurement of an electrical property of the tissue. In an example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least two conductive structures, each having a non-linear configuration, where the at least two conductive structures are disposed substantially parallel to each other. In another example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least one inductor structure.

Abstract: A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity suicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact.

Abstract: A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity silicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact.

Abstract: A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.

Abstract: A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.

Abstract: Proteins which are upregulated in injured or regenerating tissues, as well as the DNA encoding these proteins, are disclosed, as well as therapeutic compositions and methods of treatment encompassing these compounds.

Abstract: Proteins which are upregulated in injured or regenerating tissues, as well as the DNA encoding these proteins, are disclosed, as well as therapeutic compositions and methods of treatment encompassing these compounds.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: A method of fabricating a phase shift mask (PSM) is described. A patterned photoresist layer is formed on an opaque layer over a transparent plate. A thin mask layer is formed on the sidewalls of the patterned photoresist layer. The exposed opaque layer and transparent plate thereunder are then removed while using the patterned photoresist layer and mask layer as a mask. A phase shift opening is formed in the transparent plate, and thereby a phase shift layer is formed at the place where the phase shift opening is located. The patterned photoresist layer and the opaque layer thereunder are then removed to expose the transparent plate. The opaque layer under the mask layer can precisely self-align the phase shift layer to prevent alignment deviation caused by multiple lithography processes. The precision of the phase shift mask can be increased, and mask manufacture cost can be lowered.

Abstract: Proteins which are upregulated in injured or regenerating tissues, as well as the DNA encoding these proteins, are disclosed, as well as therapeutic compositions and methods of treatment encompassing these compounds.

Abstract: A method of forming dual salicides for integrated circuits. A mask layer is formed over a substrate having a first transistor and a second transistor thereon. The top surface of the first transistor's gate is higher than that of the second transistors' gate. The mask layer is patterned to expose the top surface of the second transistor's gate, source and drain. First metal suicides are formed respectively on the top surfaces of the second transistor's gate, source and drain. A dielectric layer is formed over the substrate, and the top surface of the dielectric layer is higher than that of the first transistor's gate. The dielectric layer, higher than the top surface of the second transistor's gate, is removed to expose the top surfaces of the first and the second transistors' gates. A second metal silicide is formed on the top surface of the first transistor's gate.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: The present invention discloses a method for manufacturing an array structure in integrated circuits (IC). The method for manufacturing an array structure in integrated circuits of the present invention is performed by using two masks. First, a first mask having array pattern of holes is used to perform a first exposing step with a partial dose, and a second mask having code patterns is used to perform a second exposing step with a compensating dose for the first exposing step, so that a photoresist covering the regions of the holes desired to be opened obtains a sufficient exposure dose and the holes desired are formed by developing. Therefore, a preferred resolution and a preferred depth of focus (DOF) for exposure are obtained, thereby reducing optical proximity effect (OPE), and it is quite easily to manufacture the masks used in the present invention.

Abstract: A method and structure for interconnection fabrication by using dielectric anti-reflection coating to improve the photolithographic process. The device's structure comprises a substrate with a Cu or Cu-based alloy formed therein. After planarizing the device, a thin barrier dielectric layer is formed on the substrate. A dielectric anti-reflection coating (DARC) layer is then formed on the barrier dielectric layer. Next, another inter-layer dielectric is formed on the anti-reflective coating layer and a subsequent photoresist layer is formed on the inter-reflection coating layer and patterned by using the underlying DARC layer to reduce the light reflection. By using the structure and method of the present invention, it is possible to decrease the process steps and increase the precision of the photolithographic process.

Abstract: A method of forming dual salicides for integrated circuits. A mask layer is formed over a substrate having a first transistor and a second transistor thereon. The top surface of the first transistor's gate is higher than that of the second transistors' gate. The mask layer is patterned to expose the top surface of the second transistor's gate, source and drain. First metal suicides are formed respectively on the top surfaces of the second transistor's gate, source and drain. A dielectric layer is formed over the substrate, and the top surface of the dielectric layer is higher than that of the first transistor's gate. The dielectric layer, higher than the top surface of the second transistor's gate, is removed to expose the top surfaces of the first and the second transistors' gates. A second metal silicide is formed on the top surface of the first transistor's gate.