Abstract: Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.

Abstract: An acoustic imaging system includes multiple transducers disposed to circumscribe a portion of substrate. An acoustic imaging system also includes a controller and an image resolver. The transducers convert electrical signals into mechanical energy and/or mechanical energy into electrical signals. The controller is adapted to apply an electrical signal to the transducers which, in response, induce a mechanical wave, such as a surface wave, into the circumscribed portion. The controller is also adapted to receive electrical signals from the transducers. The image resolver uses the electrical signals received by the controller in order to construct an image of an object in physical contact with the substrate.

Abstract: Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.

Abstract: A non-volatile memory device includes a plurality of wordlines, each comprising a plurality of cells, a hard decode configured to read each cell of the plurality of cells at a hard decode voltage, a left read sense configured to read voltage values of each cell to the left of the hard decode voltage at a left read sense voltage, a right read sense configured to read voltage values of each cell to the right of the hard decode voltage at a right read sense voltage, a first combiner configured to determine a difference of voltage values read by the left read sense and right read sense to produce a dispersion signal, and a second combiner configured to determine a sum of the voltage values read by the left read sense and right read sense to produce a deviation signal.

Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

Abstract: A data storage device includes a memory device including a plurality of wordlines, each including a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a first read sense at a threshold voltage of one or more threshold voltages of each cell of a wordline of the plurality of wordlines, determine that a second read sense is required based on the first read sense, receive the second read sense, determine a deviation parameter and a dispersion parameter for an asymmetric adjustment of the left threshold voltage and the right threshold voltage, and adjust the left threshold voltage and the right threshold voltage based on the deviation parameter and the dispersion parameter. The second read sense includes a plurality of left read senses at a left threshold voltage and a plurality of right senses at a right threshold voltage.

Abstract: A data storage device includes a memory device including a plurality of wordlines, each wordline having a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a plurality of left read senses and a plurality of right read senses for the plurality of cells of a wordline, determine a plurality of first windows and a plurality of second windows, determine a left window sum and a right window sum, determine a deviation parameter and a dispersion parameter based on the left window sum and the right window sum, and determine one or more characteristics of the plurality of cells based on the deviation parameter and the dispersion parameter. The deviation parameter and the dispersion parameter are used to describe a number of errors of the left read sense and the right read sense.

Abstract: A non-volatile memory device includes a plurality of wordlines, each comprising a plurality of cells, a hard decode configured to read each cell of the plurality of cells at a hard decode voltage, a left read sense configured to read voltage values of each cell to the left of the hard decode voltage at a left read sense voltage, a right read sense configured to read voltage values of each cell to the right of the hard decode voltage at a right read sense voltage, a first combiner configured to determine a difference of voltage values read by the left read sense and right read sense to produce a dispersion signal, and a second combiner configured to determine a sum of the voltage values read by the left read sense and right read sense to produce a deviation signal.

Abstract: A data storage device includes a memory device including a plurality of wordlines, each including a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a first read sense at a threshold voltage of one or more threshold voltages of each cell of a wordline of the plurality of wordlines, determine that a second read sense is required based on the first read sense, receive the second read sense, determine a deviation parameter and a dispersion parameter for an asymmetric adjustment of the left threshold voltage and the right threshold voltage, and adjust the left threshold voltage and the right threshold voltage based on the deviation parameter and the dispersion parameter. The second read sense includes a plurality of left read senses at a left threshold voltage and a plurality of right senses at a right threshold voltage.

Abstract: A controller utilizes dual sense bin balancing (DSBB) to adjust a read level between memory states of an array of NAND flash memory cells. One or more iterations of DSBB may be performed to provide a read level. Each iteration of the DSBB includes performing a first sense read, performing a second sense read, determining a read error, and adjusting the initial read level. The first sense read is performed at a first offset of an initial read level of memory cells. The second sense read is performed at a second offset of the initial read level of memory cells. A read error is determined from the first sense read and the second sense read. The read level is adjusted by the read error. A read of the randomized data pattern is conducted with the adjusted read level of a last iteration of the DSBB.

Abstract: Dual sense bin balancing (DSBB) to adjust a read level between memory states of an array of NAND flash memory cells implemented in a logic circuit of a NAND flash die or in a storage device controller. Reading a randomized data pattern stored in an array of memory cells includes performing one or more iterations of a DSBB to provide a read level. Each iteration of the DSBB includes performing a first sense read, performing a second sense read, determining a read error, and adjusting the initial read level. The first sense read is performed at a first offset of an initial read level of memory cells to determine a first number of memory cells relative to the first offset. The second sense read is performed at a second offset of the initial read level of memory cells to determine a second number of memory cells relative to the second offset. A read error of the initial read level is determined from the first sense read and the second sense read.

Abstract: A method for identifying cell coupling in a memory system includes generating a two-dimensional pseudorandom binary sequence array. The method also includes performing an erase operation on a plurality of cells of a memory block of the memory system. The method also includes performing a write operation on the plurality of cells using the two-dimensional pseudorandom binary sequence array. The method also includes performing a read operation on the plurality of cells to identify a voltage value for each cell of the plurality of cells. The method also includes identifying cell coupling between respective cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells.

Abstract: A method for identifying cell coupling in a memory system includes generating a two-dimensional pseudorandom binary sequence array. The method also includes performing an erase operation on a plurality of cells of a memory block of the memory system. The method also includes performing a write operation on the plurality of cells using the two-dimensional pseudorandom binary sequence array. The method also includes performing a read operation on the plurality of cells to identify a voltage value for each cell of the plurality of cells. The method also includes identifying cell coupling between respective cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells.