Abstract: Determining a time-state metric includes receiving a stream of raw data values of an attribute. Each received raw data value of the attribute is associated with a timestamp. It further includes converting the received stream of raw data values into a timeline representation of the attribute over time. The timeline representation comprises a sequence of spans. A span comprises a span start time, a span end time, and a span value. The span value comprises an encoding of one or more values of the attribute over a time interval determined by the span start time and the span end time. It further includes determining a time-state metric according to a timeline request configuration. The timeline request configuration comprises one or more timeline operations. The time-state metric is computed at least in part by performing a timeline operation on the timeline representation of the attribute.

Abstract: Disclosures relate to a sensor system and arrangements having different sized removable spacers. The spacers may be mixed and matched as needed or desired to compensate for misalignment conditions. Further, different spacer combinations and adjustments may be guided by a security management computing device. Variations in configurations of mounting surfaces, such as door and window assemblies, may be accommodated. Alignment of a transmitter or a receiving device, e.g., a magnetic device, with respect to a transmitter or receiving device despite misalignment of the components due to, for example, uneven surfaces of a door or a window, or a respective frame may be achieved.

Abstract: A system is disclosed that includes a computer. The computer includes a processor and a memory. The memory includes instructions such that the processor is programmed to: group a plurality of endpoints based on evaluation result data for each endpoint of the plurality of endpoints; determine a target system configuration for the group; and transmit the target system configuration to a software agent corresponding to each endpoint of the plurality of endpoints.

Abstract: A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.

Abstract: A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.

Abstract: A mixer assembly for an exhaust aftertreatment system includes a first support ring. The first support ring defines a plurality of first slots angularly spaced apart from each other. A second support ring spaced apart from the first support ring defines a plurality of second slots angularly spaced apart from each other. A plurality of blades extends between the first support ring and the second support ring. Each of the plurality of blades is coupled to each of the first support ring and the second support ring. Each of the plurality of blades includes a base. The base includes a first connecting portion engaged with a corresponding first slot from the plurality of first slots and a second connecting portion engaged with a corresponding second slot from the plurality of second slots. At least one tab extends outwardly from the base at an angle relative to the base.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queuing storage operations. An integrated circuit memory element receives a storage operation command associated with a bank of storage locations of a memory element. An integrated circuit memory element queues a storage operation command for execution on a bank of storage locations by determining a storage location in a page register for data associated with the storage operation command. A storage location in a page register includes a subset of available storage locations in the page register. An integrated circuit memory element stores data associated with a storage operation command at a determined storage location in a page register.

Abstract: Systems, methods, and vehicles for use with internal combustion engines comprising combustion chambers that produce exhaust gases that include a Stirling engine having a hot side and a cold side with the hot side being in thermal contact with exhaust gases produced by the internal combustion engine. The Stirling engine is configured to be powered by heat from the exhaust gases during operation of the internal combustion engine, and a compressor powered by the Stirling engine is configured to provide compressed air to combustion chambers of the internal combustion engine.

Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

Abstract: A lift for transferring a user to and from a vehicle, the lift including a lift platform for receiving the user, the lift platform being arcuately movable between a first position and a second position; a vertical arm coupled to the lift platform, the vertical arm having a profile that is progressively convex along the entire length of the vertical arm; and a pair of parallel arms extending from the vertical arm, wherein each of the parallel arms is pivotally coupled to a bracket mounted to the vehicle; wherein the vertical arm has a generally U-shaped cross-section that forms a channel configured to receive at least a portion of the pair of parallel arms.

Abstract: A switched resonant power converter includes multiple switching transistors, a resonant circuit comprising a capacitor and an inductor, and an auxiliary soft-start bypass circuit that bypasses a default switching path that includes a first switching transistor of the switching transistors, and provides an alternative path through an impedance element. A corresponding control circuit is configured to switch between an operational mode in which the default switching path is periodically activated while the alternative path is deactivated to provide a first frequency-responsive power through the resonant circuit, and a soft-start mode in which the alternative path is periodically activated while the default switching path is deactivated to provide a second frequency-responsive power through the resonant circuit.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

Abstract: A power interface device includes a main switching converter and an auxiliary switching converter. The main switching converter is coupled to an input terminal and an output terminal and configured to operate at a first switching frequency to source a low frequency current from the input terminal to the output terminal. The auxiliary switching converter is coupled to the input terminal and the output terminal in parallel with the main switching converter and configured to operate at a second and higher switching frequency than the first switching frequency to source a fast transient high frequency current from the input terminal to the output terminal.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queuing storage operations. An integrated circuit memory element receives a storage operation command associated with a bank of storage locations of a memory element. An integrated circuit memory element queues a storage operation command for execution on a bank of storage locations by determining a storage location in a page register for data associated with the storage operation command. A storage location in a page register includes a subset of available storage locations in the page register. An integrated circuit memory element stores data associated with a storage operation command at a determined storage location in a page register.

Abstract: A lift for transferring a user to and from a vehicle, the lift including a lift platform for receiving the user, the lift platform being arcuately movable between a first position and a second position; a vertical arm coupled to the lift platform, the vertical arm having a profile that is progressively convex along the entire length of the vertical arm; and a pair of parallel arms extending from the vertical arm, wherein each of the parallel arms is pivotally coupled to a bracket mounted to the vehicle; wherein the vertical arm has a generally U-shaped cross-section that forms a channel configured to receive at least a portion of the pair of parallel arms.

Abstract: A power interface device includes a main switching converter and an auxiliary switching converter. The main switching converter is coupled to an input terminal and an output terminal and configured to operate at a first switching frequency to source a low frequency current from the input terminal to the output terminal. The auxiliary switching converter is coupled to the input terminal and the output terminal in parallel with the main switching converter and configured to operate at a second and higher switching frequency than the first switching frequency to source a fast transient high frequency current from the input terminal to the output terminal.

Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

Abstract: Systems and methods described herein presents a PaaS level application or app motion system that manages and moves applications between multiple PaaS instances in a hybrid cloud that includes both private and public cloud instances. Specifically, the system performs an app motion operation on an application by cloning, moving, and/or scaling up the application from one PaaS instance to one or more other PaaS instances in the hybrid cloud. Since the system achieves application mobility and scalability at the PaaS level by only moving the application and its associated data between the PaaS instances without moving the virtual machines (VMs), it could greatly reduce the amount of data transmitted during the process and save both time and network resources. It also enables enterprises to extend their applications from a private cloud to a public cloud and uniformly manage the applications cross the boundaries of the clouds.