Patents by Inventor Heny Lin
Heny Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9892997Abstract: A semiconductor package includes at least one semiconductor device situated on a leadframe island, a first at least one lead protruding from a first side of the semiconductor package and configured to provide a first electrical connection to at least one terminal of the at least one semiconductor device, a second at least one lead protruding from a second side of the semiconductor package and configured to provide a second electrical connection to the at least one terminal of the at least one semiconductor device, and a continuous conductive structure configured to provide a conductive path between the first at least one lead, the second at least one lead, and the at least one terminal of the at least one semiconductor device through the leadframe island such that the at least one semiconductor device continues to function after trimming the first at least one lead.Type: GrantFiled: April 19, 2016Date of Patent: February 13, 2018Assignee: Infineon Technologies Americas Corp.Inventors: Heny Lin, Katsumi Okawa
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Publication number: 20170301613Abstract: A semiconductor package includes at least one semiconductor device situated on a leadframe island, a first at least one lead protruding from a first side of the semiconductor package and configured to provide a first electrical connection to at least one terminal of the at least one semiconductor device, a second at least one lead protruding from a second side of the semiconductor package and configured to provide a second electrical connection to the at least one terminal of the at least one semiconductor device, and a continuous conductive structure configured to provide a conductive path between the first at least one lead, the second at least one lead, and the at least one terminal of the at least one semiconductor device through the leadframe island such that the at least one semiconductor device continues to function after trimming the first at least one lead.Type: ApplicationFiled: April 19, 2016Publication date: October 19, 2017Inventors: Heny Lin, Katsumi Okawa
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Patent number: 9530774Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.Type: GrantFiled: February 12, 2015Date of Patent: December 27, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Heny Lin, Jason Zhang, Alberto Guerra
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Patent number: 9312245Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.Type: GrantFiled: September 25, 2014Date of Patent: April 12, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Heny Lin, Jason Zhang, Alberto Guerra
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Publication number: 20150162326Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.Type: ApplicationFiled: February 12, 2015Publication date: June 11, 2015Inventors: Heny Lin, Jason Zhang, Alberto Guerra
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Patent number: 8963338Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.Type: GrantFiled: March 22, 2011Date of Patent: February 24, 2015Assignee: International Rectifier CorporationInventors: Heny Lin, Jason Zhang, Alberto Guerra
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Publication number: 20150008445Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.Type: ApplicationFiled: September 25, 2014Publication date: January 8, 2015Inventors: Heny Lin, Jason Zhang, Alberto Guerra
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Patent number: 8847408Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.Type: GrantFiled: March 22, 2011Date of Patent: September 30, 2014Assignee: International Rectifier CorporationInventors: Heny Lin, Jason Zhang, Alberto Guerra
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Publication number: 20120223321Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.Type: ApplicationFiled: March 22, 2011Publication date: September 6, 2012Applicant: INTERNATIONAL RECTIFIER CORPORATIONInventors: Heny Lin, Jason Zhang, Alberto Guerra
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Publication number: 20120223322Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.Type: ApplicationFiled: March 22, 2011Publication date: September 6, 2012Applicant: INTERNATIONAL RECTIFIER CORPORATIONInventors: Heny Lin, Jason Zhang, Alberto Guerra
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Publication number: 20070257343Abstract: A high voltage semiconductor module has a leadframe with spaced pads which is connected to a heat sink plate by a curable insulation layer on the top of the plate. Semiconductor die may be soldered to the leadframe pads before or after assembly to the plate. The insulation layer may be a curable epoxy or a B stage IMS plate.Type: ApplicationFiled: May 3, 2007Publication date: November 8, 2007Inventors: Henning M. Hauenstein, Jack Marcinkowski, Heny Lin
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Publication number: 20060290689Abstract: A power module that includes embedded power bus bars and output bus arranged to lower the parasitic inductance.Type: ApplicationFiled: June 26, 2006Publication date: December 28, 2006Inventors: William Grant, Heny Lin, Jack Marcinkowski, Velimir Nedic
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Patent number: 7149088Abstract: A power module which includes heatsinks made of AlSiC and power semiconductor devices directly mounted thereon.Type: GrantFiled: June 18, 2004Date of Patent: December 12, 2006Assignee: International Rectifier CorporationInventors: Heny Lin, Bertrand Vaysse, Fabio Necco
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Patent number: 7042730Abstract: A power module including a power circuit having heat generating power devices including one or more heatsinks not isolated from the power devices by an insulating body.Type: GrantFiled: July 31, 2003Date of Patent: May 9, 2006Assignee: International Rectifier CorporationInventors: Bertrand Vaysse, Heny Lin, Thanh Van Tran, Ajit Dubhashi
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Publication number: 20050280998Abstract: A power module which includes heatsinks made of AlSiC and power semiconductor devices directly mounted thereon.Type: ApplicationFiled: June 18, 2004Publication date: December 22, 2005Inventors: Heny Lin, Bertrand Vaysse, Fabio Necco
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Publication number: 20040095729Abstract: power module including a power circuit having heat generating power devices including one or more heatsinks not isolated from the power devices by an insulating body.Type: ApplicationFiled: July 31, 2003Publication date: May 20, 2004Inventors: Bertrand Vaysse, Heny Lin, Thanh Van Tran, Ajit Dubhashi