Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a substrate chuck, a shower head structure over the substrate chuck, and a gas distribution apparatus connected to the shower head structure. The gas distribution apparatus includes a dispersion container including a first dispersion space and a gas inlet section on the dispersion container. The gas inlet section includes a first inlet pipe including a first inlet path fluidly connected to the first dispersion space and a second inlet pipe including a second inlet path fluidly connected to the first dispersion space. The second inlet pipe surrounds at least a portion of a sidewall of the first inlet pipe.

Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a substrate chuck, a shower head structure over the substrate chuck, and a gas distribution apparatus connected to the shower head structure. The gas distribution apparatus includes a dispersion container including a first dispersion space and a gas inlet section on the dispersion container. The gas inlet section includes a first inlet pipe including a first inlet path fluidly connected to the first dispersion space and a second inlet pipe including a second inlet path fluidly connected to the first dispersion space. The second inlet pipe surrounds at least a portion of a sidewall of the first inlet pipe.

Abstract: A gate all around field effect transistor (GAAFET) device may include a plurality of nanostructures that are spaced apart from one another in a channel region of the FET device above a substrate. A gate electrode can be in a GAA arrangement with the plurality of nanostructures and a semiconductor pattern can be on one side of the gate electrode. A contact in a contact trench in the semiconductor pattern and a silicide film can extend conformally on a side wall of the contact trench to a level in the channel region that is lower an uppermost one of the plurality of nanostructures.

Abstract: A split gate trench field effect transistor includes a gate electrode formed in a trench. A shield gate is formed in a trench below the gate electrode and surrounded by an insulating structure to float the shield electrode.

Abstract: A split gate trench field effect transistor includes a gate electrode formed in a trench. A shield gate is formed in a trench below the gate electrode and surrounded by an insulating structure to float the shield electrode.

Abstract: A semiconductor device can include first and second vertical channel power MOSFET transistors that are arranged in a split-gate configuration in a semiconductor substrate. A groove can be in an active region between the first and second vertical channel power MOSFET transistors and a conductive pattern can be in the groove on the active region, where the conductive pattern can include a source contact for the first and second vertical channel power MOSFET transistors. A vertical Schottky semiconductor region can be embedded in the groove beneath the conductive pattern between the vertical channels.

Abstract: A power semiconductor device is provided. The power semiconductor device includes a source electrode disposed on a device activation region and widened in a direction toward a first side, a drain electrode arranged alternately with the source electrode on the device activation region and widened in a direction toward a second side facing the first side, an insulating layer disposed on the source electrode and the drain electrode and configured to include a plurality of via contacts contacting the source electrode and the drain electrode, a source electrode pad disposed in a first region on the insulating layer to be brought into contact with the source electrode, and a drain electrode pad disposed in a second region separated from the first region on the insulating layer and brought into contact with the plurality of via contacts contacting the drain electrode.

Abstract: A power semiconductor device is provided. The power semiconductor device includes a source electrode disposed on a device activation region and widened in a direction toward a first side, a drain electrode arranged alternately with the source electrode on the device activation region and widened in a direction toward a second side facing the first side, an insulating layer disposed on the source electrode and the drain electrode and configured to include a plurality of via contacts contacting the source electrode and the drain electrode, a source electrode pad disposed in a first region on the insulating layer to be brought into contact with the source electrode, and a drain electrode pad disposed in a second region separated from the first region on the insulating layer and brought into contact with the plurality of via contacts contacting the drain electrode.