Abstract: An apparatus includes a first set of scan-enabled flip-flop circuits may be configured to shift a scan-chain pattern from a first test input node to a first test output node using a first clock signal. A particular lockup latch may be coupled to the first test output node and to a second test input node. This particular lockup latch may be configured to, when enabled, delay propagation of the scan-chain pattern from the first test output node to the second test input node. A second set of scan-enabled flip-flop circuits may be configured to shift the scan-chain pattern from the second test input node to a second test output node using a second clock signal, different from the first clock signal. A control circuit may be configured to determine whether to enable the particular lockup latch using a particular scan test signal.

Abstract: In some embodiments, an apparatus includes conductors, and a transmitter including transmitter test circuitry to embed test properties in test pattern signals, and transmit the test pattern signals to the conductors. In some embodiments, an apparatus includes conductors to carry test pattern signals with embedded test properties, and receiver test circuitry to receive the test pattern signals and extract the test properties and determine whether the extracted test properties match expected test properties. Other embodiments are described and claimed.

Abstract: In some embodiments, an apparatus includes conductors, and a transmitter including transmitter test circuitry to embed test properties in test pattern signals, and transmit the test pattern signals to the conductors. In some embodiments, an apparatus includes conductors to carry test pattern signals with embedded test properties, and receiver test circuitry to receive the test pattern signals and extract the test properties and determine whether the extracted test properties match expected test properties. Other embodiments are described and claimed.