Abstract: A light cylinder, a dispenser, and a method of manufacturing a light cylinder are disclosed. The light cylinder includes an outer layer and an inside layer, where the inside layer is formed by filling optical resin into the inside space of the outer layer, and the refractive index of the optical resin is determined in consideration of the refractive index of the outer layer.

Abstract: A light device using a light cylinder is disclosed. The light device includes a cover, a light source section combined with at least part of an inside surface of the cover and configured to output a light, and a light cylinder configured to include one entrance part and a plurality of output parts. The entrance part is combined with the light source section, and the light incident through the entrance part is outputted through the output parts.

Abstract: A charging status indicator of an electric vehicle installed at one side of a charging status indicator cover to indicate a charging status of the electric vehicle as an illumination may include a lens-integrated lamp housing and a printed circuit board (PCB) housing which are vertically coupled to each other, a PCB installed in the PCB housing and having a plurality of Light Emitting Diodes (LEDs) mounted thereon, and a diffusion cap diffusing LED.

Abstract: A light device using a light cylinder is disclosed. The light device includes a cover, a light source section combined with one or more sides of inside sides of the cover and configured to output a light, and a light cylinder configured to include one entrance part and plural output parts. Here, the entrance part is combined with the light source section, and the light incident through the entrance part is outputted through the output parts.

Abstract: A charging status indicator of an electric vehicle installed at one side of a charging status indicator cover to indicate a charging status of the electric vehicle as an illumination may include a lens-integrated lamp housing and a printed circuit board (PCB) housing which are vertically coupled to each other, a PCB installed in the PCB housing and having a plurality of Light Emitting Diodes (LEDs) mounted thereon, and a diffusion cap diffusing LED.

Abstract: A light cylinder, a dispenser, and a method of manufacturing a light cylinder are disclosed. The light cylinder includes an outer layer and an inside layer, where the inside layer is formed by filling optical resin into the inside space of the outer layer, and the refractive index of the optical resin is determined in consideration of the refractive index of the outer layer.

Abstract: A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test data is derived at least partially from the address data generated from the linear feedback shift register.

Abstract: An integrated circuit semiconductor device comprises a built-in self-repair (BISR) circuit including a plurality of row fill entries and a plurality of column fill entries for storing faulty memory cell information of an embedded memory. Sizes of the row and column fill entries are determined by the numbers of row and column redundancies of the embedded memory. The row/column fill entries store row/column addresses of the faulty memory cells, and the number of the faulty memory cells occurring at the same row/column address, respectively. In addition, the row/column fill entries include pointers for indicating opposite entries storing the column/row address corresponding to the row/column address. For repairing the faulty memory cells with the row and column redundancies, the BISR circuit selects row/column fill entries and deletes the number of the fault memory cells stored in the opposite fill entry.

Abstract: Integrated circuit devices have a self-test capability in which a sequence of input data patterns are generated by a test pattern unit and are selectively applied to a functional or test block that is selected from a plurality of potential test blocks. The output data patterns that are generated by the selected test block are provided to a data compression unit that generates a signature in response thereto. This signature can then be compared with an expected pattern to determine whether the selected test block is functioning properly. Because the test pattern unit and the data compression unit are shared by a plurality of test blocks, the area normally reserved for test circuitry in an integrated circuit device can be reduced.

Abstract: A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test data is derived at least partially from the address data generated from the linear feedback shift register.

Abstract: A memory address generating apparatus and method of a dynamic memory testing circuit for generating addresses for testing a dynamic memory which uses all the available addresses of the dynamic memory, which does not use the most significant addresses, and which does not use middle addresses among all the available addresses are provided. The address generator can obtain an up-counted address by up counting the addresses used by the dynamic memory. It can obtain a down-counted address by inverting the N-bit up-counted value, or by subtracting the N-bit up-counted value from the maximum address, or by combining the inverted MSB portion of the N-bit up-counted value with the LSB portion of the N-bit up-counted value subtracted from the LSB portion of the maximum address used in the dynamic memory. The down and up counted addresses are used as addresses for selectively testing the dynamic memory according to a selected testing method.

Abstract: A memory address generating apparatus and method of a dynamic memory testing circuit for generating addresses for testing a dynamic memory which uses all the available addresses of the dynamic memory, which does not use the most significant addresses, and which does not use middle addresses among all the available addresses are provided. The address generator can obtain an up-counted address by up counting the addresses used by the dynamic memory. It can obtain a down-counted address by inverting the N-bit up-counted value, or by subtracting the N-bit up-counted value from the maximum address, or by combining the inverted MSB portion of the N-bit up-counted value with the LSB portion of the N-bit up-counted value subtracted from the LSB portion of the maximum address used in the dynamic memory. The down and up counted addresses are used as addresses for selectively testing the dynamic memory according to a selected testing method.

Abstract: A memory address generator having a small chip area, a method for generating a memory address and a SRAM built-in self test (BIST) circuit using the same are described. When the number of addresses of a memory to be tested is 2.sup.n, where n is the number of bits in an address, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses, and an inverter for inverting the first address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to a control signal, to output the selected address as an address of the memory. When the number of addresses of the memory to be tested is not 2.sup.

Abstract: A built-in self test (BIST) circuit using a linear feedback shift register (LFSR) and a multiple input signature register (MISR) requiring reduced circuitry exclusive of the number of inputs and outputs of the circuit to be tested. The BIST circuit is built in a prescribed circuit having a memory to test a target circuit in the prescribed circuit.

Abstract: A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

Abstract: A serial memory interface includes a register having a plurality of flip-flops forming a scan chain and coupled to both the input and output terminals of memory cells. An interlaced scan is established by interconnecting scan chains between multiple memory blocks. The interface structure provides a means for efficiently performing a built-in self test of an embedded memory while requiring minimal overhead in hardware structure.

Abstract: The present invention provides a test method of SOA (Single-Order Addressed) memory utilizing address data backgrounds applied to memory circuits. A memory test operation is performed using a total of (log.sub.2 N+1) address data backgrounds on an SOA memory having N mutually different addresses. Each address data background is written and read, then the inversion is written and read. Finally the address data background is again written and read for a total of 6 N(log.sub.2 N+1) operations.