Abstract: A method for forming a contact hole in a semiconductor device, capable of obtaining a good step coverage in formation of metal wiring and contacts of a highly integrated circuit exhibiting a high topology. The method comprises a primary etching step including the steps of forming a first mask pattern on an insulating film and etching the insulating film by use of the first mask pattern such that a possibly largest area of the insulating film is etched in so far as conduction layers present in the insulating film are not exposed, thereby reducing a topology at an upper portion of the contact region, and a secondary etching step including the steps of removing the first mask pattern, forming a second mask pattern for exposing the contact region, and etching the insulating film remaining over the contact region by use of the second mask, thereby forming a contact hole.

Abstract: A method for manufacturing a planarized metal layer on a wafer of a semiconductor device by providing a wafer and sequentially depositing a conducting layer 1 and an insulating layer 2 on the wafer 10 is described. A contact hole is formed in a portion of the insulating layer 2 exposing a portion of the underlying conducting layer 1 and simultaneously forming a step difference. The resulting wafer 10 comprising the contact hole is placed into a first chamber and heated in order to degas the insulating layer 2 and a first metal layer 3 is deposited on the degassed insulating layer 2 and on the contact hole 5 to a thickness of about 10 to 50% of the desired predetermined final thickness. The resulting wafer comprising the first metal layer is placed into a second chamber and heated. A second metal layer 4 is then deposited on the first metal layer 3 to a thickness of about 50 to 90% of the desired predetermined final thickness to provide a planarized metal layer.