Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.

Abstract: A non-volatile memory device includes gate stack structures formed on a semiconductor substrate to be separated by a first space in a first area and by a second wider space in a second area adjacent to the first area. First gate spacers of a low dielectric constant insulating material are formed on the sidewalls of the gate stack structures. Second gate spacers made of an insulating material having good step coverage are formed on the first gate spacers to fill the first space. This dual spacer structure comprising the first gate spacer and the second gate spacer prevents the creation of void between gates. Thus, it can prevent an active region from being opened in a subsequent etching process and preclude the formation of a silicide layer on the active region. Thus, the device characteristics can be substantially improved.

Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.