Abstract: The present invention provides: a negative electrode active material having high discharge capacity, high charge output, and excellent discharge output characteristics; and a carbon material therefor. A carbon material for a negative electrode active material according to an embodiment of the present invention provides a carbon material having the total fibrosity index (TFI) of 0.58 to 0.78.

Abstract: A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.

Abstract: An internal reference voltage generation device may include a cell array including a plurality of cells which provide reference voltages of different levels. Each of the plurality of cells may include one of a plurality of divider resistors included in a resistor string; a transmission gate configured to output a voltage of a divider node which is connected to the one divider resistor, in response to a select signal; and a unit decoder configured to provide the select signal to the transmission gate.

Abstract: A pipe register includes: a plurality of register units configured to output data in response to control signals; and a pipe control circuit configured to generate a reference timing signal by dividing a clock signal, the clock signal activated during an activation time of a read enable signal, and generate the control signals based on the read enable signal and the reference timing signal.

Abstract: A clock transmission circuit includes a clock driver circuit suitable for transmitting a clock and adjusting a driving force thereof in response to a boosting signal; a low-pass filter circuit suitable for receiving the clock and outputting an initialization signal; and a boosting signal generating circuit suitable for generating the boosting signal that is activated in response to the initialization signal and deactivated in response to the clock.

Abstract: A clock transmission circuit includes a clock driver circuit suitable for transmitting a clock and adjusting a driving force thereof in response to a boosting signal; a low-pass filter circuit suitable for receiving the clock and outputting an initialization signal; and a boosting signal generating circuit suitable for generating the boosting signal that is activated in response to the initialization signal and deactivated in response to the clock.

Abstract: The present technology relates to a memory device that generates various signals used in a read training operation and a method of operating the memory device. The memory device according to an embodiment of the present disclosure includes an address counter configured to generate a plurality of count signals based on a read training enable signal and a first clock signal received from a memory controller, and an address section identification signal generator configured to generate address section identification signals used in identifying a plurality of address sections based on at least one of the plurality of count signals.

Abstract: The present technology relates to a memory device that generates various signals used in a read training operation and a method of operating the memory device. The memory device according to an embodiment of the present disclosure includes an address counter configured to generate a plurality of count signals based on a read training enable signal and a first clock signal received from a memory controller, and an address section identification signal generator configured to generate address section identification signals used in identifying a plurality of address sections based on at least one of the plurality of count signals.