Abstract: In manufacturing a thin film transistor array substrate, a passivation film is formed over the transistors. A first photoresist pattern is formed over the passivation film, with a first portion partially overlying at least one source/drain electrode of each transistor and overlying each pixel electrode region, and with a second portion thicker than the first portion. The passivation film is patterned using the first photoresist pattern as a mask. The first photoresist pattern's first portion is removed to form a second photoresist pattern which protrudes upward around the pixel electrode regions. A transparent conductive film is formed with recesses in the pixel electrode regions. A masking pattern is formed over the transparent film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent film. The transparent film is patterned using the masking pattern as a mask to form the pixel electrodes.

Abstract: In manufacturing a thin film transistor array substrate, a passivation film is formed over the transistors. A first photoresist pattern is formed over the passivation film, with a first portion partially overlying at least one source/drain electrode of each transistor and overlying each pixel electrode region, and with a second portion thicker than the first portion. The passivation film is patterned using the first photoresist pattern as a mask. The first photoresist pattern's first portion is removed to form a second photoresist pattern which protrudes upward around the pixel electrode regions. A transparent conductive film is formed with recesses in the pixel electrode regions. A masking pattern is formed over the transparent film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent film. The transparent film is patterned using the masking pattern as a mask to form the pixel electrodes.

Abstract: A touch screen display apparatus includes a first substrate including a pixel electrode and a lower sensor electrode, a second substrate facing the first substrate and including a common electrode and an upper sensor electrode facing the lower sensor electrode, a liquid crystal layer interposed between the substrates, a first alignment layer disposed on the pixel electrode and the common electrode, a second alignment layer disposed on the lower sensor electrode, and a third alignment layer disposed on the upper sensor electrode. The second or third alignment layers aligns the liquid crystal layer in a different direction from a direction the first alignment layer aligns the liquid crystal layer. When pressure is applied onto a point on the first or second substrate, a distance and a capacitance between the lower sensor electrode and the upper sensor electrode at the point are changed to detect a position of the point.

Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

Abstract: For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.

Abstract: Disclosed is a liquid crystal display apparatus including a first substrate, a second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. A pixel area is defined on the first substrate. A pixel electrode includes a cut-out pattern and is formed in the pixel area. A conductive pattern is disposed between the first substrate and the pixel electrode, and partially overlaps the cut-out pattern when viewed from a plan view. A common electrode is disposed on the second substrate and includes a domain divider dividing the pixel area into a plurality of domains. A light blocking member is disposed on one of the first substrate and the second substrate, and is positioned corresponding to a portion of areas in which the cut-out pattern overlaps the conductive pattern within the pixel area.

Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

Abstract: According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.

Abstract: The present invention provides an optical film that includes i) a (meth)acrylic resin, and 5 to 45 parts by weight of ii) a graft copolymer, prepared by grafting a (meth)acrylic resin onto a copolymer of (meth)acrylic rubber and aromatic vinyl compound, based on 100 parts by weight of the i) (meth)acrylic resin, and an electronic device including the optical film.

Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

Abstract: The present invention relates to an enteric, sustained-release tablet comprising paroxetine or a hydrates or anhydrides of a pharmaceutically acceptable salt thereof as active substance, more particularly to a tablet prepared by coating a sustained-release tablet core containing paroxetine with an enteric polymer, wherein the interaction between the tablet core and the enteric coating layer is minimized to enable constant drug release without regard to the residence time of the tablet in the stomach.

Abstract: Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its formation using the current photolithography-etching technique may be readily formed.

Abstract: In a semiconductor device having a resistor and a method of fabricating the same, the device includes a semiconductor substrate having a cell region and a peripheral region. A lower interlayer insulating layer is disposed on the semiconductor substrate. A buffer pad is disposed on the lower interlayer insulating layer in the cell region. A capacitor is provided to have a storage node electrode disposed on the buffer pad, a plate electrode covering the storage node electrode, and a capacitor dielectric is interposed between the storage node electrode and the plate electrode. A lower resistor is disposed on the lower interlayer insulating layer in the peripheral region. An upper resistor is disposed on the lower resistor to expose both ends of the lower resistor. An inter-resistor insulating layer is interposed at least between the lower resistor and the upper resistor.

Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punchthrough protection layer and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line pattern fills an upper portion of the channel-portion hole, and is formed on the semiconductor substrate. The word line pattern is formed to have a word line and a word line capping layer pattern stacked thereon, and the channel-portion layer is a channel region. The punchthrough protection layer can reduce a leakage current of a capacitor of the transistor embodied in a DRAM.

Abstract: This invention relates to a solid dispersion formulation comprising tacrolimus and enteric polymer. The solid dispersion formulation may contribute to better stability of tacrolimus preparation under high temperature and humidity condition through reduced recrystallization rate of tacrolimus. In addition, the solid dispersion formulation releases tacrolimus immediately in aqueous media and elevated solubility level maintains for certain period of time and that way the formulation may also enhance the bioavailability and oral absorption rate of tacrolimus.

Abstract: An array substrate includes a gate line part, a data line part, a pixel portion, at least one test transistor, and a test pad part. The gate line part is formed along a first direction, and includes gate lines and at least one dummy gate line. The data line part is formed along a second direction crossing the first direction, and includes data lines and at least one dummy data line. The pixel portion is electrically connected to the gate lines and the data lines. At least one test transistor is electrically connected to the dummy gate line and the dummy data line. The test pad part is electrically connected to the dummy gate line, the dummy data line and a drain electrode of the test transistor.

Abstract: A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

Abstract: According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to extend over a main surface of the semiconductor substrate. Source/drain regions having a first conductivity are disposed in the active region at both sides of the channel trench. A channel impurity region having a second conductivity is disposed beneath one of the source/drain regions to be in contact with at least a sidewall of the channel trench.

Abstract: Disclosed is a liquid crystal display apparatus including a first substrate, a second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. A pixel area is defined on the first substrate. A pixel electrode includes a cut-out pattern and is formed in the pixel area. A conductive pattern is disposed between the first substrate and the pixel electrode, and partially overlaps the cut-out pattern when viewed from a plan view. A common electrode is disposed on the second substrate and includes a domain divider dividing the pixel area into a plurality of domains. A light blocking member is disposed on one of the first substrate and the second substrate, and is positioned corresponding to a portion of areas in which the cut-out pattern overlaps the conductive pattern within the pixel area.

Abstract: A method of fabricating a semiconductor device, including forming contact pads in a first insulating layer on a substrate, forming a second insulating layer on the first insulating layer and on the contact pads, forming bit lines on the second insulating layer, the bit lines connected to a first plurality of the contact pads by bit line contact plugs, forming expanded contact holes in the second insulating layer between the bit lines, wherein the expanded contact holes are expanded toward the bit lines, and forming contact spacers on side walls of the expanded contact holes.