Abstract: An extension to existent vector instruction sets is presented in a form of new vector instructions which perform operations specialized for efficient digital video compression and decompression. A processor is designed to implement the arithmetic operation of each of these instructions in a single clock cycle, and some of the present instructions perform arithmetic operations selectively and directly on elements of the same registers.

Abstract: A vector processor includes two banks of vector registers where each vector register can stored multiple data elements and a control register with a field indicating a default bank. An instruction set for the vector processor includes instructions which use a register number to identify a vector registers in the default bank, uses a register number to identify a double-size vector register including a register from the first bank and a register from the second bank, and instructions which include a bank bit and a register number to access a vector register from either bank.

Abstract: Instruction issue rate is enhanced by passing multiple instructions to a read stage when the number of required source operands exceeds the read capability of a register file but operand forwarding reduces the number of reads required. The multiple instructions can be issued for execution with source operands read from the register file and source operands forwarded from execution units without using maximum number of register file read ports in a superscalar vector processor architecture. Even when there is both inter-instruction data dependency and there are more source operands for, say, two instructions, to be fetched than available register file read ports, if some of the source operands can be obtained via result forwarding and the rest of the operands can be obtained via available register file read ports, the two instructions can be issued simultaneously.

Abstract: Video data compression techniques reduce necessary storage size and communication channel bandwidth while maintaining acceptable fidelity. Vector quantization provides better overall data compression performance by coding vectors instead of scalars. The search algorithm and VLSI architecture for implementing it is herein disclosed, and such a search algorithm is useful for real-time image processing. The architecture employs a single processing element and external memory for storing the N constant value hyperplanes used in the search, where N is the number of codevectors. The design does not perform any multiplication operation using the constant value hyperplane tree search, since the tree search method is independent of any L.sub.q metric for q between one and infinity. Memory used by the design is significantly less than memory employed in existing architecture.