Abstract: A semiconductor package includes; an interposer mounted on a package substrate, a first semiconductor device and a second semiconductor device mounted on the interposer, a molding member including an outer side wall portion covering an outer side surface of the first semiconductor device, and a lower portion covering at least a portion of an upper surface of the interposer, and a capping structure including an outer side wall portion covering the outer side wall portion of the molding member.

Abstract: A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.

Abstract: A semiconductor package includes an interposer substrate on a package substrate. The interposer substrate includes an upper pad on an upper surface of the insulating layer, a lower pad on a lower surface of the insulating layer, and a redistribution structure penetrating the insulating layer between the upper surface and the lower surface to connect the upper pad and the lower pad. A semiconductor chip is disposed above the interposer substrate and connected to the upper pad, and a connection bump directly contacts a lower surface of the lower pad. The redistribution structure includes redistribution layers and redistribution vias connected to the redistribution layers, wherein each of the redistribution layers and each of the redistribution vias includes a metal material layer and a plating seed layer, and the lower pad directly contacts the plating seed layer.

Abstract: A semiconductor package includes; an interposer mounted on a package substrate, a first semiconductor device and a second semiconductor device mounted on the interposer, a molding member including an outer side wall portion covering an outer side surface of the first semiconductor device, and a lower portion covering at least a portion of an upper surface of the interposer, and a capping structure including an outer side wall portion covering the outer side wall portion of the molding member.

Abstract: A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.

Abstract: A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.